* ChibiOS conf upgrade for akegata_denki/device_one akegata_denki/device_one -pull/11607/head0d9f891416
* ChibiOS conf upgrade for chavdai40 chavdai40/rev1 -06bca6ec34
chavdai40/rev2 -f55650a8d7
* ChibiOS conf upgrade for ergodox_stm32 ergodox_stm32 -04433b80e4
* ChibiOS conf upgrade for jm60 jm60 -a127e6cfcc
* ChibiOS conf upgrade for matrix/m20add matrix/m20add -e2e556dad6
* ChibiOS conf upgrade for matrix/noah matrix/noah -c6fd3caf0b
@ -1,263 +0,0 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
/* | |||
* This file has been automatically generated using ChibiStudio board | |||
* generator plugin. Do not edit manually. | |||
*/ | |||
#include <hal.h> | |||
#include <stm32_gpio.h> | |||
/*===========================================================================*/ | |||
/* Driver local definitions. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver exported variables. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver local variables and types. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Type of STM32 GPIO port setup. | |||
*/ | |||
typedef struct { | |||
uint32_t moder; | |||
uint32_t otyper; | |||
uint32_t ospeedr; | |||
uint32_t pupdr; | |||
uint32_t odr; | |||
uint32_t afrl; | |||
uint32_t afrh; | |||
} gpio_setup_t; | |||
/** | |||
* @brief Type of STM32 GPIO initialization data. | |||
*/ | |||
typedef struct { | |||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__) | |||
gpio_setup_t PAData; | |||
#endif | |||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__) | |||
gpio_setup_t PBData; | |||
#endif | |||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__) | |||
gpio_setup_t PCData; | |||
#endif | |||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__) | |||
gpio_setup_t PDData; | |||
#endif | |||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__) | |||
gpio_setup_t PEData; | |||
#endif | |||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__) | |||
gpio_setup_t PFData; | |||
#endif | |||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__) | |||
gpio_setup_t PGData; | |||
#endif | |||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__) | |||
gpio_setup_t PHData; | |||
#endif | |||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__) | |||
gpio_setup_t PIData; | |||
#endif | |||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) | |||
gpio_setup_t PJData; | |||
#endif | |||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__) | |||
gpio_setup_t PKData; | |||
#endif | |||
} gpio_config_t; | |||
/** | |||
* @brief STM32 GPIO static initialization data. | |||
*/ | |||
static const gpio_config_t gpio_default_config = { | |||
#if STM32_HAS_GPIOA | |||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, | |||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOB | |||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, | |||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOC | |||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, | |||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOD | |||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, | |||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOE | |||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, | |||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOF | |||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, | |||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOG | |||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, | |||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOH | |||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, | |||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOI | |||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, | |||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOJ | |||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, | |||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOK | |||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, | |||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} | |||
#endif | |||
}; | |||
/*===========================================================================*/ | |||
/* Driver local functions. */ | |||
/*===========================================================================*/ | |||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { | |||
gpiop->OTYPER = config->otyper; | |||
gpiop->OSPEEDR = config->ospeedr; | |||
gpiop->PUPDR = config->pupdr; | |||
gpiop->ODR = config->odr; | |||
gpiop->AFRL = config->afrl; | |||
gpiop->AFRH = config->afrh; | |||
gpiop->MODER = config->moder; | |||
} | |||
static void stm32_gpio_init(void) { | |||
/* Enabling GPIO-related clocks, the mask comes from the | |||
registry header file.*/ | |||
rccResetAHB(STM32_GPIO_EN_MASK); | |||
rccEnableAHB(STM32_GPIO_EN_MASK, true); | |||
/* Initializing all the defined GPIO ports.*/ | |||
#if STM32_HAS_GPIOA | |||
gpio_init(GPIOA, &gpio_default_config.PAData); | |||
#endif | |||
#if STM32_HAS_GPIOB | |||
gpio_init(GPIOB, &gpio_default_config.PBData); | |||
#endif | |||
#if STM32_HAS_GPIOC | |||
gpio_init(GPIOC, &gpio_default_config.PCData); | |||
#endif | |||
#if STM32_HAS_GPIOD | |||
gpio_init(GPIOD, &gpio_default_config.PDData); | |||
#endif | |||
#if STM32_HAS_GPIOE | |||
gpio_init(GPIOE, &gpio_default_config.PEData); | |||
#endif | |||
#if STM32_HAS_GPIOF | |||
gpio_init(GPIOF, &gpio_default_config.PFData); | |||
#endif | |||
#if STM32_HAS_GPIOG | |||
gpio_init(GPIOG, &gpio_default_config.PGData); | |||
#endif | |||
#if STM32_HAS_GPIOH | |||
gpio_init(GPIOH, &gpio_default_config.PHData); | |||
#endif | |||
#if STM32_HAS_GPIOI | |||
gpio_init(GPIOI, &gpio_default_config.PIData); | |||
#endif | |||
#if STM32_HAS_GPIOJ | |||
gpio_init(GPIOJ, &gpio_default_config.PJData); | |||
#endif | |||
#if STM32_HAS_GPIOK | |||
gpio_init(GPIOK, &gpio_default_config.PKData); | |||
#endif | |||
} | |||
/*===========================================================================*/ | |||
/* Driver interrupt handlers. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver exported functions. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Early initialization code. | |||
* @details GPIO ports and system clocks are initialized before everything | |||
* else. | |||
*/ | |||
void __early_init(void) { | |||
stm32_gpio_init(); | |||
stm32_clock_init(); | |||
} | |||
#if HAL_USE_SDC || defined(__DOXYGEN__) | |||
/** | |||
* @brief SDC card detection. | |||
*/ | |||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { | |||
(void)sdcp; | |||
/* TODO: Fill the implementation.*/ | |||
return true; | |||
} | |||
/** | |||
* @brief SDC card write protection detection. | |||
*/ | |||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) { | |||
(void)sdcp; | |||
/* TODO: Fill the implementation.*/ | |||
return false; | |||
} | |||
#endif /* HAL_USE_SDC */ | |||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) | |||
/** | |||
* @brief MMC_SPI card detection. | |||
*/ | |||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { | |||
(void)mmcp; | |||
/* TODO: Fill the implementation.*/ | |||
return true; | |||
} | |||
/** | |||
* @brief MMC_SPI card write protection detection. | |||
*/ | |||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) { | |||
(void)mmcp; | |||
/* TODO: Fill the implementation.*/ | |||
return false; | |||
} | |||
#endif | |||
/** | |||
* @brief Board-specific initialization code. | |||
* @todo Add your board-specific code, if any. | |||
*/ | |||
void boardInit(void) { | |||
} |
@ -1,950 +0,0 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
/* | |||
* This file has been automatically generated using ChibiStudio board | |||
* generator plugin. Do not edit manually. | |||
*/ | |||
#ifndef BOARD_H | |||
#define BOARD_H | |||
/*===========================================================================*/ | |||
/* Driver constants. */ | |||
/*===========================================================================*/ | |||
/* | |||
* Setup for STMicroelectronics STM32 Nucleo32-F042K6 board. | |||
*/ | |||
/* | |||
* Board identifier. | |||
*/ | |||
#define BOARD_ST_NUCLEO32_F042K6 | |||
#define BOARD_NAME "STMicroelectronics STM32 Nucleo32-F042K6" | |||
/* | |||
* Board oscillators-related settings. | |||
* NOTE: LSE not fitted. | |||
* NOTE: HSE not fitted. | |||
*/ | |||
#if !defined(STM32_LSECLK) | |||
#define STM32_LSECLK 0U | |||
#endif | |||
#define STM32_LSEDRV (3U << 3U) | |||
#if !defined(STM32_HSECLK) | |||
#define STM32_HSECLK 0U | |||
#endif | |||
/* | |||
* MCU type as defined in the ST header. | |||
*/ | |||
#define STM32F042x6 | |||
/* | |||
* IO pins assignments. | |||
*/ | |||
#define GPIOA_ARD_A0 0U | |||
#define GPIOA_ARD_A1 1U | |||
#define GPIOA_VCP_TX 2U | |||
#define GPIOA_ARD_A2 3U | |||
#define GPIOA_ARD_A3 4U | |||
#define GPIOA_ARD_A4 5U | |||
#define GPIOA_ARD_A5 6U | |||
#define GPIOA_ARD_A6 7U | |||
#define GPIOA_ARD_D9 8U | |||
#define GPIOA_ARD_D1 9U | |||
#define GPIOA_ARD_D0 10U | |||
#define GPIOA_ARD_D10 11U | |||
#define GPIOA_ARD_D2 12U | |||
#define GPIOA_SWDIO 13U | |||
#define GPIOA_SWCLK 14U | |||
#define GPIOA_VCP_RX 15U | |||
#define GPIOB_ARD_D3 0U | |||
#define GPIOB_ARD_D6 1U | |||
#define GPIOB_PIN2 2U | |||
#define GPIOB_ARD_D13 3U | |||
#define GPIOB_LED_GREEN 3U | |||
#define GPIOB_ARD_D12 4U | |||
#define GPIOB_ARD_D11 5U | |||
#define GPIOB_ARD_D5 6U | |||
#define GPIOB_ARD_A5_ALT 6U | |||
#define GPIOB_ARD_D4 7U | |||
#define GPIOB_ARD_A4_ALT 7U | |||
#define GPIOB_PIN8 8U | |||
#define GPIOB_PIN9 9U | |||
#define GPIOB_PIN10 10U | |||
#define GPIOB_PIN11 11U | |||
#define GPIOB_PIN12 12U | |||
#define GPIOB_PIN13 13U | |||
#define GPIOB_PIN14 14U | |||
#define GPIOB_PIN15 15U | |||
#define GPIOC_PIN0 0U | |||
#define GPIOC_PIN1 1U | |||
#define GPIOC_PIN2 2U | |||
#define GPIOC_PIN3 3U | |||
#define GPIOC_PIN4 4U | |||
#define GPIOC_PIN5 5U | |||
#define GPIOC_PIN6 6U | |||
#define GPIOC_PIN7 7U | |||
#define GPIOC_PIN8 8U | |||
#define GPIOC_PIN9 9U | |||
#define GPIOC_PIN10 10U | |||
#define GPIOC_PIN11 11U | |||
#define GPIOC_PIN12 12U | |||
#define GPIOC_PIN13 13U | |||
#define GPIOC_PIN14 14U | |||
#define GPIOC_PIN15 15U | |||
#define GPIOD_PIN0 0U | |||
#define GPIOD_PIN1 1U | |||
#define GPIOD_PIN2 2U | |||
#define GPIOD_PIN3 3U | |||
#define GPIOD_PIN4 4U | |||
#define GPIOD_PIN5 5U | |||
#define GPIOD_PIN6 6U | |||
#define GPIOD_PIN7 7U | |||
#define GPIOD_PIN8 8U | |||
#define GPIOD_PIN9 9U | |||
#define GPIOD_PIN10 10U | |||
#define GPIOD_PIN11 11U | |||
#define GPIOD_PIN12 12U | |||
#define GPIOD_PIN13 13U | |||
#define GPIOD_PIN14 14U | |||
#define GPIOD_PIN15 15U | |||
#define GPIOE_PIN0 0U | |||
#define GPIOE_PIN1 1U | |||
#define GPIOE_PIN2 2U | |||
#define GPIOE_PIN3 3U | |||
#define GPIOE_PIN4 4U | |||
#define GPIOE_PIN5 5U | |||
#define GPIOE_PIN6 6U | |||
#define GPIOE_PIN7 7U | |||
#define GPIOE_PIN8 8U | |||
#define GPIOE_PIN9 9U | |||
#define GPIOE_PIN10 10U | |||
#define GPIOE_PIN11 11U | |||
#define GPIOE_PIN12 12U | |||
#define GPIOE_PIN13 13U | |||
#define GPIOE_PIN14 14U | |||
#define GPIOE_PIN15 15U | |||
#define GPIOF_ARD_D7 0U | |||
#define GPIOF_ARD_D8 1U | |||
#define GPIOF_PIN2 2U | |||
#define GPIOF_PIN3 3U | |||
#define GPIOF_PIN4 4U | |||
#define GPIOF_PIN5 5U | |||
#define GPIOF_PIN6 6U | |||
#define GPIOF_PIN7 7U | |||
#define GPIOF_PIN8 8U | |||
#define GPIOF_PIN9 9U | |||
#define GPIOF_PIN10 10U | |||
#define GPIOF_PIN11 11U | |||
#define GPIOF_PIN12 12U | |||
#define GPIOF_PIN13 13U | |||
#define GPIOF_PIN14 14U | |||
#define GPIOF_PIN15 15U | |||
/* | |||
* IO lines assignments. | |||
*/ | |||
#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) | |||
#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) | |||
#define LINE_VCP_TX PAL_LINE(GPIOA, 2U) | |||
#define LINE_ARD_A2 PAL_LINE(GPIOA, 3U) | |||
#define LINE_ARD_A3 PAL_LINE(GPIOA, 4U) | |||
#define LINE_ARD_A4 PAL_LINE(GPIOA, 5U) | |||
#define LINE_ARD_A5 PAL_LINE(GPIOA, 6U) | |||
#define LINE_ARD_A6 PAL_LINE(GPIOA, 7U) | |||
#define LINE_ARD_D9 PAL_LINE(GPIOA, 8U) | |||
#define LINE_ARD_D1 PAL_LINE(GPIOA, 9U) | |||
#define LINE_ARD_D0 PAL_LINE(GPIOA, 10U) | |||
#define LINE_ARD_D10 PAL_LINE(GPIOA, 11U) | |||
#define LINE_ARD_D2 PAL_LINE(GPIOA, 12U) | |||
#define LINE_SWDIO PAL_LINE(GPIOA, 13U) | |||
#define LINE_SWCLK PAL_LINE(GPIOA, 14U) | |||
#define LINE_VCP_RX PAL_LINE(GPIOA, 15U) | |||
#define LINE_ARD_D3 PAL_LINE(GPIOB, 0U) | |||
#define LINE_ARD_D6 PAL_LINE(GPIOB, 1U) | |||
#define LINE_ARD_D13 PAL_LINE(GPIOB, 3U) | |||
#define LINE_LED_GREEN PAL_LINE(GPIOB, 3U) | |||
#define LINE_ARD_D12 PAL_LINE(GPIOB, 4U) | |||
#define LINE_ARD_D11 PAL_LINE(GPIOB, 5U) | |||
#define LINE_ARD_D5 PAL_LINE(GPIOB, 6U) | |||
#define LINE_ARD_A5_ALT PAL_LINE(GPIOB, 6U) | |||
#define LINE_ARD_D4 PAL_LINE(GPIOB, 7U) | |||
#define LINE_ARD_A4_ALT PAL_LINE(GPIOB, 7U) | |||
#define LINE_ARD_D7 PAL_LINE(GPIOF, 0U) | |||
#define LINE_ARD_D8 PAL_LINE(GPIOF, 1U) | |||
/*===========================================================================*/ | |||
/* Driver pre-compile time settings. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Derived constants and error checks. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver data structures and types. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver macros. */ | |||
/*===========================================================================*/ | |||
/* | |||
* I/O ports initial setup, this configuration is established soon after reset | |||
* in the initialization code. | |||
* Please refer to the STM32 Reference Manual for details. | |||
*/ | |||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) | |||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) | |||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) | |||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) | |||
#define PIN_ODR_LOW(n) (0U << (n)) | |||
#define PIN_ODR_HIGH(n) (1U << (n)) | |||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) | |||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) | |||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) | |||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) | |||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) | |||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) | |||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) | |||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) | |||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) | |||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) | |||
/* | |||
* GPIOA setup: | |||
* | |||
* PA0 - ARD_A0 (input pullup). | |||
* PA1 - ARD_A1 (input pullup). | |||
* PA2 - VCP_TX (alternate 1). | |||
* PA3 - ARD_A2 (input pullup). | |||
* PA4 - ARD_A3 (input pullup). | |||
* PA5 - ARD_A4 (input pullup). | |||
* PA6 - ARD_A5 (input pullup). | |||
* PA7 - ARD_A6 (input pullup). | |||
* PA8 - ARD_D9 (input pullup). | |||
* PA9 - ARD_D1 (input pullup). | |||
* PA10 - ARD_D0 (input pullup). | |||
* PA11 - ARD_D10 (input pullup). | |||
* PA12 - ARD_D2 (input pullup). | |||
* PA13 - SWDIO (alternate 0). | |||
* PA14 - SWCLK (alternate 0). | |||
* PA15 - VCP_RX (alternate 1). | |||
*/ | |||
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ARD_A0) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_A1) | \ | |||
PIN_MODE_ALTERNATE(GPIOA_VCP_TX) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_A2) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_A3) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_A4) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_A5) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_A6) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_D9) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_D1) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_D0) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_D10) | \ | |||
PIN_MODE_INPUT(GPIOA_ARD_D2) | \ | |||
PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ | |||
PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ | |||
PIN_MODE_ALTERNATE(GPIOA_VCP_RX)) | |||
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_VCP_TX) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_A3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_A4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_A5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_A6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_D9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_D10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_VCP_RX)) | |||
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ | |||
PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ | |||
PIN_OSPEED_LOW(GPIOA_VCP_TX) | \ | |||
PIN_OSPEED_LOW(GPIOA_ARD_A2) | \ | |||
PIN_OSPEED_HIGH(GPIOA_ARD_A3) | \ | |||
PIN_OSPEED_LOW(GPIOA_ARD_A4) | \ | |||
PIN_OSPEED_HIGH(GPIOA_ARD_A5) | \ | |||
PIN_OSPEED_HIGH(GPIOA_ARD_A6) | \ | |||
PIN_OSPEED_HIGH(GPIOA_ARD_D9) | \ | |||
PIN_OSPEED_HIGH(GPIOA_ARD_D1) | \ | |||
PIN_OSPEED_HIGH(GPIOA_ARD_D0) | \ | |||
PIN_OSPEED_HIGH(GPIOA_ARD_D10) | \ | |||
PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \ | |||
PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ | |||
PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ | |||
PIN_OSPEED_HIGH(GPIOA_VCP_RX)) | |||
#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \ | |||
PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_A3) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_A4) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_A5) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_A6) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_D9) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_D1) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_D0) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_D10) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_ARD_D2) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ | |||
PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ | |||
PIN_PUPDR_FLOATING(GPIOA_VCP_RX)) | |||
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \ | |||
PIN_ODR_HIGH(GPIOA_ARD_A1) | \ | |||
PIN_ODR_HIGH(GPIOA_VCP_TX) | \ | |||
PIN_ODR_HIGH(GPIOA_ARD_A2) | \ | |||
PIN_ODR_HIGH(GPIOA_ARD_A3) | \ | |||
PIN_ODR_LOW(GPIOA_ARD_A4) | \ | |||
PIN_ODR_HIGH(GPIOA_ARD_A5) | \ | |||
PIN_ODR_HIGH(GPIOA_ARD_A6) | \ | |||
PIN_ODR_HIGH(GPIOA_ARD_D9) | \ | |||
PIN_ODR_HIGH(GPIOA_ARD_D1) | \ | |||
PIN_ODR_HIGH(GPIOA_ARD_D0) | \ | |||
PIN_ODR_HIGH(GPIOA_ARD_D10) | \ | |||
PIN_ODR_HIGH(GPIOA_ARD_D2) | \ | |||
PIN_ODR_HIGH(GPIOA_SWDIO) | \ | |||
PIN_ODR_HIGH(GPIOA_SWCLK) | \ | |||
PIN_ODR_HIGH(GPIOA_VCP_RX)) | |||
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_VCP_TX, 1U) | \ | |||
PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_ARD_A3, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_ARD_A4, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_ARD_A5, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_ARD_A6, 0U)) | |||
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D9, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_ARD_D1, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_ARD_D0, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_ARD_D10, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_VCP_RX, 1U)) | |||
/* | |||
* GPIOB setup: | |||
* | |||
* PB0 - ARD_D3 (input pullup). | |||
* PB1 - ARD_D6 (input pullup). | |||
* PB2 - PIN2 (input pullup). | |||
* PB3 - ARD_D13 LED_GREEN (output pushpull maximum). | |||
* PB4 - ARD_D12 (input pullup). | |||
* PB5 - ARD_D11 (input pullup). | |||
* PB6 - ARD_D5 ARD_A5_ALT (input pullup). | |||
* PB7 - ARD_D4 ARD_A4_ALT (input pullup). | |||
* PB8 - PIN8 (input pullup). | |||
* PB9 - PIN9 (input pullup). | |||
* PB10 - PIN10 (input pullup). | |||
* PB11 - PIN11 (input pullup). | |||
* PB12 - PIN12 (input pullup). | |||
* PB13 - PIN13 (input pullup). | |||
* PB14 - PIN14 (input pullup). | |||
* PB15 - PIN15 (input pullup). | |||
*/ | |||
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_ARD_D3) | \ | |||
PIN_MODE_INPUT(GPIOB_ARD_D6) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN2) | \ | |||
PIN_MODE_OUTPUT(GPIOB_ARD_D13) | \ | |||
PIN_MODE_INPUT(GPIOB_ARD_D12) | \ | |||
PIN_MODE_INPUT(GPIOB_ARD_D11) | \ | |||
PIN_MODE_INPUT(GPIOB_ARD_D5) | \ | |||
PIN_MODE_INPUT(GPIOB_ARD_D4) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN15)) | |||
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) | |||
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_D3) | \ | |||
PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN2) | \ | |||
PIN_OSPEED_HIGH(GPIOB_ARD_D13) | \ | |||
PIN_OSPEED_HIGH(GPIOB_ARD_D12) | \ | |||
PIN_OSPEED_HIGH(GPIOB_ARD_D11) | \ | |||
PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \ | |||
PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN8) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN9) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN11) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN12) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN13) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN14) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN15)) | |||
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ARD_D3) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_ARD_D6) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ | |||
PIN_PUPDR_FLOATING(GPIOB_ARD_D13) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_ARD_D12) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_ARD_D11) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN15)) | |||
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_D3) | \ | |||
PIN_ODR_HIGH(GPIOB_ARD_D6) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN2) | \ | |||
PIN_ODR_LOW(GPIOB_ARD_D13) | \ | |||
PIN_ODR_HIGH(GPIOB_ARD_D12) | \ | |||
PIN_ODR_HIGH(GPIOB_ARD_D11) | \ | |||
PIN_ODR_HIGH(GPIOB_ARD_D5) | \ | |||
PIN_ODR_HIGH(GPIOB_ARD_D4) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN15)) | |||
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_ARD_D13, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_ARD_D12, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_ARD_D11, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_ARD_D4, 0U)) | |||
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN15, 0U)) | |||
/* | |||
* GPIOC setup: | |||
* | |||
* PC0 - PIN0 (input pullup). | |||
* PC1 - PIN1 (input pullup). | |||
* PC2 - PIN2 (input pullup). | |||
* PC3 - PIN3 (input pullup). | |||
* PC4 - PIN4 (input pullup). | |||
* PC5 - PIN5 (input pullup). | |||
* PC6 - PIN6 (input pullup). | |||
* PC7 - PIN7 (input pullup). | |||
* PC8 - PIN8 (input pullup). | |||
* PC9 - PIN9 (input pullup). | |||
* PC10 - PIN10 (input pullup). | |||
* PC11 - PIN11 (input pullup). | |||
* PC12 - PIN12 (input pullup). | |||
* PC13 - PIN13 (input pullup). | |||
* PC14 - PIN14 (input pullup). | |||
* PC15 - PIN15 (input pullup). | |||
*/ | |||
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN1) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN2) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN3) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN4) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN5) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN6) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN7) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN15)) | |||
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) | |||
#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN1) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN2) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN3) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN4) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN5) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN6) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN7) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN8) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN9) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN11) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN12) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN13) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN14) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN15)) | |||
#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN15)) | |||
#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN1) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN2) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN3) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN4) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN5) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN6) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN7) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN15)) | |||
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN7, 0U)) | |||
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN15, 0U)) | |||
/* | |||
* GPIOD setup: | |||
* | |||
* PD0 - PIN0 (input pullup). | |||
* PD1 - PIN1 (input pullup). | |||
* PD2 - PIN2 (input pullup). | |||
* PD3 - PIN3 (input pullup). | |||
* PD4 - PIN4 (input pullup). | |||
* PD5 - PIN5 (input pullup). | |||
* PD6 - PIN6 (input pullup). | |||
* PD7 - PIN7 (input pullup). | |||
* PD8 - PIN8 (input pullup). | |||
* PD9 - PIN9 (input pullup). | |||
* PD10 - PIN10 (input pullup). | |||
* PD11 - PIN11 (input pullup). | |||
* PD12 - PIN12 (input pullup). | |||
* PD13 - PIN13 (input pullup). | |||
* PD14 - PIN14 (input pullup). | |||
* PD15 - PIN15 (input pullup). | |||
*/ | |||
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN1) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN2) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN3) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN4) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN5) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN6) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN7) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN15)) | |||
#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) | |||
#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN1) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN2) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN3) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN4) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN5) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN6) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN7) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN8) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN9) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN11) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN12) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN13) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN14) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN15)) | |||
#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN15)) | |||
#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN1) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN2) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN3) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN4) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN5) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN6) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN7) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN15)) | |||
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN7, 0U)) | |||
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN15, 0U)) | |||
/* | |||
* GPIOE setup: | |||
* | |||
* PE0 - PIN0 (input pullup). | |||
* PE1 - PIN1 (input pullup). | |||
* PE2 - PIN2 (input pullup). | |||
* PE3 - PIN3 (input pullup). | |||
* PE4 - PIN4 (input pullup). | |||
* PE5 - PIN5 (input pullup). | |||
* PE6 - PIN6 (input pullup). | |||
* PE7 - PIN7 (input pullup). | |||
* PE8 - PIN8 (input pullup). | |||
* PE9 - PIN9 (input pullup). | |||
* PE10 - PIN10 (input pullup). | |||
* PE11 - PIN11 (input pullup). | |||
* PE12 - PIN12 (input pullup). | |||
* PE13 - PIN13 (input pullup). | |||
* PE14 - PIN14 (input pullup). | |||
* PE15 - PIN15 (input pullup). | |||
*/ | |||
#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN1) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN2) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN3) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN4) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN5) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN6) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN7) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN15)) | |||
#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) | |||
#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN1) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN2) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN3) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN4) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN5) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN6) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN7) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN8) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN9) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN11) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN12) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN13) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN14) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN15)) | |||
#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN15)) | |||
#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN1) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN2) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN3) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN4) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN5) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN6) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN7) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN15)) | |||
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN7, 0U)) | |||
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN15, 0U)) | |||
/* | |||
* GPIOF setup: | |||
* | |||
* PF0 - ARD_D7 (input pullup). | |||
* PF1 - ARD_D8 (input pullup). | |||
* PF2 - PIN2 (input pullup). | |||
* PF3 - PIN3 (input pullup). | |||
* PF4 - PIN4 (input pullup). | |||
* PF5 - PIN5 (input pullup). | |||
* PF6 - PIN6 (input pullup). | |||
* PF7 - PIN7 (input pullup). | |||
* PF8 - PIN8 (input pullup). | |||
* PF9 - PIN9 (input pullup). | |||
* PF10 - PIN10 (input pullup). | |||
* PF11 - PIN11 (input pullup). | |||
* PF12 - PIN12 (input pullup). | |||
* PF13 - PIN13 (input pullup). | |||
* PF14 - PIN14 (input pullup). | |||
* PF15 - PIN15 (input pullup). | |||
*/ | |||
#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_ARD_D7) | \ | |||
PIN_MODE_INPUT(GPIOF_ARD_D8) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN2) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN3) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN4) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN5) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN6) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN7) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN15)) | |||
#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_ARD_D7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_ARD_D8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) | |||
#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_ARD_D7) | \ | |||
PIN_OSPEED_HIGH(GPIOF_ARD_D8) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN2) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN3) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN4) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN5) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN6) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN7) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN8) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN9) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN11) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN12) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN13) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN14) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN15)) | |||
#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_ARD_D7) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_ARD_D8) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN15)) | |||
#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_ARD_D7) | \ | |||
PIN_ODR_HIGH(GPIOF_ARD_D8) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN2) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN3) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN4) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN5) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN6) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN7) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN15)) | |||
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_ARD_D7, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_ARD_D8, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN7, 0U)) | |||
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN15, 0U)) | |||
/*===========================================================================*/ | |||
/* External declarations. */ | |||
/*===========================================================================*/ | |||
#if !defined(_FROM_ASM_) | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
void boardInit(void); | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* _FROM_ASM_ */ | |||
#endif /* BOARD_H */ |
@ -1,5 +0,0 @@ | |||
# List of all the board related files. | |||
BOARDSRC = $(BOARD_PATH)/boards/DEVICE_ONE/board.c | |||
# Required include directories | |||
BOARDINC = $(BOARD_PATH)/boards/DEVICE_ONE |
@ -1,266 +0,0 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
/* | |||
* This file has been automatically generated using ChibiStudio board | |||
* generator plugin. Do not edit manually. | |||
*/ | |||
#include <hal.h> | |||
#include <stm32_gpio.h> | |||
/*===========================================================================*/ | |||
/* Driver local definitions. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver exported variables. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver local variables and types. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Type of STM32 GPIO port setup. | |||
*/ | |||
typedef struct { | |||
uint32_t moder; | |||
uint32_t otyper; | |||
uint32_t ospeedr; | |||
uint32_t pupdr; | |||
uint32_t odr; | |||
uint32_t afrl; | |||
uint32_t afrh; | |||
} gpio_setup_t; | |||
/** | |||
* @brief Type of STM32 GPIO initialization data. | |||
*/ | |||
typedef struct { | |||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__) | |||
gpio_setup_t PAData; | |||
#endif | |||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__) | |||
gpio_setup_t PBData; | |||
#endif | |||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__) | |||
gpio_setup_t PCData; | |||
#endif | |||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__) | |||
gpio_setup_t PDData; | |||
#endif | |||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__) | |||
gpio_setup_t PEData; | |||
#endif | |||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__) | |||
gpio_setup_t PFData; | |||
#endif | |||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__) | |||
gpio_setup_t PGData; | |||
#endif | |||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__) | |||
gpio_setup_t PHData; | |||
#endif | |||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__) | |||
gpio_setup_t PIData; | |||
#endif | |||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) | |||
gpio_setup_t PJData; | |||
#endif | |||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__) | |||
gpio_setup_t PKData; | |||
#endif | |||
} gpio_config_t; | |||
/** | |||
* @brief STM32 GPIO static initialization data. | |||
*/ | |||
static const gpio_config_t gpio_default_config = { | |||
#if STM32_HAS_GPIOA | |||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, | |||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOB | |||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, | |||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOC | |||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, | |||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOD | |||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, | |||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOE | |||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, | |||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOF | |||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, | |||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOG | |||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, | |||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOH | |||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, | |||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOI | |||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, | |||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOJ | |||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, | |||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOK | |||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, | |||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} | |||
#endif | |||
}; | |||
/*===========================================================================*/ | |||
/* Driver local functions. */ | |||
/*===========================================================================*/ | |||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { | |||
gpiop->OTYPER = config->otyper; | |||
gpiop->OSPEEDR = config->ospeedr; | |||
gpiop->PUPDR = config->pupdr; | |||
gpiop->ODR = config->odr; | |||
gpiop->AFRL = config->afrl; | |||
gpiop->AFRH = config->afrh; | |||
gpiop->MODER = config->moder; | |||
} | |||
static void stm32_gpio_init(void) { | |||
/* Enabling GPIO-related clocks, the mask comes from the | |||
registry header file.*/ | |||
rccResetAHB(STM32_GPIO_EN_MASK); | |||
rccEnableAHB(STM32_GPIO_EN_MASK, true); | |||
/* Initializing all the defined GPIO ports.*/ | |||
#if STM32_HAS_GPIOA | |||
gpio_init(GPIOA, &gpio_default_config.PAData); | |||
#endif | |||
#if STM32_HAS_GPIOB | |||
gpio_init(GPIOB, &gpio_default_config.PBData); | |||
#endif | |||
#if STM32_HAS_GPIOC | |||
gpio_init(GPIOC, &gpio_default_config.PCData); | |||
#endif | |||
#if STM32_HAS_GPIOD | |||
gpio_init(GPIOD, &gpio_default_config.PDData); | |||
#endif | |||
#if STM32_HAS_GPIOE | |||
gpio_init(GPIOE, &gpio_default_config.PEData); | |||
#endif | |||
#if STM32_HAS_GPIOF | |||
gpio_init(GPIOF, &gpio_default_config.PFData); | |||
#endif | |||
#if STM32_HAS_GPIOG | |||
gpio_init(GPIOG, &gpio_default_config.PGData); | |||
#endif | |||
#if STM32_HAS_GPIOH | |||
gpio_init(GPIOH, &gpio_default_config.PHData); | |||
#endif | |||
#if STM32_HAS_GPIOI | |||
gpio_init(GPIOI, &gpio_default_config.PIData); | |||
#endif | |||
#if STM32_HAS_GPIOJ | |||
gpio_init(GPIOJ, &gpio_default_config.PJData); | |||
#endif | |||
#if STM32_HAS_GPIOK | |||
gpio_init(GPIOK, &gpio_default_config.PKData); | |||
#endif | |||
} | |||
/*===========================================================================*/ | |||
/* Driver interrupt handlers. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver exported functions. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Early initialization code. | |||
* @details GPIO ports and system clocks are initialized before everything | |||
* else. | |||
*/ | |||
void __early_init(void) { | |||
stm32_gpio_init(); | |||
stm32_clock_init(); | |||
} | |||
#if HAL_USE_SDC || defined(__DOXYGEN__) | |||
/** | |||
* @brief SDC card detection. | |||
*/ | |||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { | |||
(void)sdcp; | |||
/* CHTODO: Fill the implementation.*/ | |||
return true; | |||
} | |||
/** | |||
* @brief SDC card write protection detection. | |||
*/ | |||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) { | |||
(void)sdcp; | |||
/* CHTODO: Fill the implementation.*/ | |||
return false; | |||
} | |||
#endif /* HAL_USE_SDC */ | |||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) | |||
/** | |||
* @brief MMC_SPI card detection. | |||
*/ | |||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { | |||
(void)mmcp; | |||
/* CHTODO: Fill the implementation.*/ | |||
return true; | |||
} | |||
/** | |||
* @brief MMC_SPI card write protection detection. | |||
*/ | |||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) { | |||
(void)mmcp; | |||
/* CHTODO: Fill the implementation.*/ | |||
return false; | |||
} | |||
#endif | |||
/** | |||
* @brief Board-specific initialization code. | |||
* @note You can add your board-specific code here. | |||
*/ | |||
void boardInit(void) { | |||
} |
@ -1,9 +0,0 @@ | |||
# List of all the board related files. | |||
BOARDSRC = $(BOARD_PATH)/boards/GENERIC_STM32_F042X6/board.c | |||
# Required include directories | |||
BOARDINC = $(BOARD_PATH)/boards/GENERIC_STM32_F042X6 | |||
# Shared variables | |||
ALLCSRC += $(BOARDSRC) | |||
ALLINC += $(BOARDINC) |
@ -0,0 +1,37 @@ | |||
/* | |||
Copyright 2021 QMK | |||
This program is free software: you can redistribute it and/or modify | |||
it under the terms of the GNU General Public License as published by | |||
the Free Software Foundation, either version 2 of the License, or | |||
(at your option) any later version. | |||
This program is distributed in the hope that it will be useful, | |||
but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
GNU General Public License for more details. | |||
You should have received a copy of the GNU General Public License | |||
along with this program. If not, see <http://www.gnu.org/licenses/>. | |||
*/ | |||
#include_next <board.h> | |||
#ifdef STM32_LSECLK | |||
#undef STM32_LSECLK | |||
#endif // STM32_LSECLK | |||
#define STM32_LSECLK 32768 | |||
#ifdef STM32_HSECLK | |||
#undef STM32_HSECLK | |||
#endif // STM32_HSECLK | |||
#define STM32_HSECLK 8000000 | |||
#undef VAL_GPIOACRL | |||
#define VAL_GPIOACRL 0x88888888 | |||
#undef VAL_GPIOAODR | |||
#define VAL_GPIOAODR 0xFFFFFFFF | |||
#undef VAL_GPIOCCRH | |||
#define VAL_GPIOCCRH 0x88888888 |
@ -1,49 +0,0 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
#include <hal.h> | |||
/** | |||
* @brief PAL setup. | |||
* @details Digital I/O ports static configuration as defined in @p board.h. | |||
* This variable is used by the HAL when initializing the PAL driver. | |||
*/ | |||
#if HAL_USE_PAL || defined(__DOXYGEN__) | |||
const PALConfig pal_default_config = | |||
{ | |||
{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, | |||
{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, | |||
{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, | |||
{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, | |||
{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, | |||
}; | |||
#endif | |||
/* | |||
* Early initialization code. | |||
* This initialization must be performed just after stack setup and before | |||
* any other initialization. | |||
*/ | |||
void __early_init(void) { | |||
stm32_clock_init(); | |||
} | |||
/* | |||
* Board-specific initialization code. | |||
*/ | |||
void boardInit(void) { | |||
} |
@ -1,142 +0,0 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
#ifndef _BOARD_H_ | |||
#define _BOARD_H_ | |||
/* | |||
* Board identifier. | |||
*/ | |||
#define BOARD_JM60 | |||
#define BOARD_NAME "ErgoDox STM32 Keyboard" | |||
/* | |||
* Board frequencies. | |||
*/ | |||
#define STM32_LSECLK 0 | |||
#define STM32_HSECLK 8000000 | |||
/* | |||
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. | |||
* | |||
* Only xB (128KB Flash) is defined, but it's identical to the | |||
* x8 version (64KB Flash) except for the Flash region size in the | |||
* linker script. For x8 parts use xB here and change to the x8 linker | |||
* script in the project Makefile. | |||
*/ | |||
#define STM32F103xB | |||
/* | |||
* IO pins assignments | |||
* | |||
* numbering is sorted by onboard/connectors, as from the schematics in | |||
* http://www.vcc-gnd.com/read.php?tid=369 | |||
*/ | |||
/* on-board */ | |||
#define GPIOA_USBDM 11 // pin 8 | |||
#define GPIOA_USBDP 12 // pin 9 | |||
#define GPIOC_OSC32_IN 14 | |||
#define GPIOC_OSC32_OUT 15 | |||
/* | |||
* I/O ports initial setup, this configuration is established soon after reset | |||
* in the initialization code. | |||
* | |||
* The digits have the following meaning: | |||
* 0 - Analog input. | |||
* 1 - Push Pull output 10MHz. | |||
* 2 - Push Pull output 2MHz. | |||
* 3 - Push Pull output 50MHz. | |||
* 4 - Digital input. | |||
* 5 - Open Drain output 10MHz. | |||
* 6 - Open Drain output 2MHz. | |||
* 7 - Open Drain output 50MHz. | |||
* 8 - Digital input with PullUp or PullDown resistor depending on ODR. | |||
* 9 - Alternate Push Pull output 10MHz. | |||
* A - Alternate Push Pull output 2MHz. | |||
* B - Alternate Push Pull output 50MHz. | |||
* C - Reserved. | |||
* D - Alternate Open Drain output 10MHz. | |||
* E - Alternate Open Drain output 2MHz. | |||
* F - Alternate Open Drain output 50MHz. | |||
* Please refer to the STM32 Reference Manual for details. | |||
*/ | |||
/* | |||
* Port A setup. | |||
* Everything input with pull-up except: | |||
*/ | |||
#define VAL_GPIOACRL 0x88888888 /* PA7...PA0 */ | |||
#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */ | |||
#define VAL_GPIOAODR 0xFFFFFFFF | |||
/* | |||
* Port B setup. | |||
* Everything input with pull-up except: | |||
*/ | |||
#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */ | |||
#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */ | |||
#define VAL_GPIOBODR 0xFFFFFFFF | |||
/* | |||
* Port C setup. | |||
* Everything input with pull-up except: | |||
*/ | |||
#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */ | |||
#define VAL_GPIOCCRH 0x88888888 /* PC15...PC8 */ | |||
#define VAL_GPIOCODR 0xFFFFFFFF | |||
/* | |||
* Port D setup. | |||
* Everything input with pull-up except: | |||
* PD0 - Normal input (XTAL). | |||
* PD1 - Normal input (XTAL). | |||
*/ | |||
#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */ | |||
#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ | |||
#define VAL_GPIODODR 0xFFFFFFFF | |||
/* | |||
* Port E setup. | |||
* Everything input with pull-up except: | |||
*/ | |||
#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ | |||
#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ | |||
#define VAL_GPIOEODR 0xFFFFFFFF | |||
/* | |||
* USB bus activation macro, required by the USB driver. | |||
*/ | |||
#define usb_lld_connect_bus(usbp) /* always connected */ | |||
/* | |||
* USB bus de-activation macro, required by the USB driver. | |||
*/ | |||
#define usb_lld_disconnect_bus(usbp) /* always connected */ | |||
#if !defined(_FROM_ASM_) | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
void boardInit(void); | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* _FROM_ASM_ */ | |||
#endif /* _BOARD_H_ */ |
@ -1,5 +0,0 @@ | |||
# List of all the board related files. | |||
BOARDSRC = $(BOARD_PATH)/boards/ERGODOX_STM32_BOARD/board.c | |||
# Required include directories | |||
BOARDINC = $(BOARD_PATH)/boards/ERGODOX_STM32_BOARD |
@ -0,0 +1,37 @@ | |||
/* | |||
Copyright 2021 QMK | |||
This program is free software: you can redistribute it and/or modify | |||
it under the terms of the GNU General Public License as published by | |||
the Free Software Foundation, either version 2 of the License, or | |||
(at your option) any later version. | |||
This program is distributed in the hope that it will be useful, | |||
but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
GNU General Public License for more details. | |||
You should have received a copy of the GNU General Public License | |||
along with this program. If not, see <http://www.gnu.org/licenses/>. | |||
*/ | |||
#include_next <board.h> | |||
#ifdef STM32_LSECLK | |||
#undef STM32_LSECLK | |||
#endif // STM32_LSECLK | |||
#define STM32_LSECLK 32768 | |||
#ifdef STM32_HSECLK | |||
#undef STM32_HSECLK | |||
#endif // STM32_HSECLK | |||
#define STM32_HSECLK 8000000 | |||
#undef VAL_GPIOACRL | |||
#define VAL_GPIOACRL 0x88888888 | |||
#undef VAL_GPIOAODR | |||
#define VAL_GPIOAODR 0xFFFFFFFF | |||
#undef VAL_GPIOCCRH | |||
#define VAL_GPIOCCRH 0x88888888 |
@ -1,49 +0,0 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
#include <hal.h> | |||
/** | |||
* @brief PAL setup. | |||
* @details Digital I/O ports static configuration as defined in @p board.h. | |||
* This variable is used by the HAL when initializing the PAL driver. | |||
*/ | |||
#if HAL_USE_PAL || defined(__DOXYGEN__) | |||
const PALConfig pal_default_config = | |||
{ | |||
{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, | |||
{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, | |||
{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, | |||
{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, | |||
{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, | |||
}; | |||
#endif | |||
/* | |||
* Early initialization code. | |||
* This initialization must be performed just after stack setup and before | |||
* any other initialization. | |||
*/ | |||
void __early_init(void) { | |||
stm32_clock_init(); | |||
} | |||
/* | |||
* Board-specific initialization code. | |||
*/ | |||
void boardInit(void) { | |||
} |
@ -1,142 +0,0 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
#ifndef _BOARD_H_ | |||
#define _BOARD_H_ | |||
/* | |||
* Board identifier. | |||
*/ | |||
#define BOARD_JM60 | |||
#define BOARD_NAME "JM60 keyboard" | |||
/* | |||
* Board frequencies. | |||
*/ | |||
#define STM32_LSECLK 32768 | |||
#define STM32_HSECLK 8000000 | |||
/* | |||
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. | |||
* | |||
* Only xB (128KB Flash) is defined, but it's identical to the | |||
* x8 version (64KB Flash) except for the Flash region size in the | |||
* linker script. For x8 parts use xB here and change to the x8 linker | |||
* script in the project Makefile. | |||
*/ | |||
#define STM32F103xB | |||
/* | |||
* IO pins assignments | |||
* | |||
* numbering is sorted by onboard/connectors, as from the schematics in | |||
* http://www.vcc-gnd.com/read.php?tid=369 | |||
*/ | |||
/* on-board */ | |||
#define GPIOA_USBDM 11 // pin 8 | |||
#define GPIOA_USBDP 12 // pin 9 | |||
#define GPIOC_OSC32_IN 14 | |||
#define GPIOC_OSC32_OUT 15 | |||
/* | |||
* I/O ports initial setup, this configuration is established soon after reset | |||
* in the initialization code. | |||
* | |||
* The digits have the following meaning: | |||
* 0 - Analog input. | |||
* 1 - Push Pull output 10MHz. | |||
* 2 - Push Pull output 2MHz. | |||
* 3 - Push Pull output 50MHz. | |||
* 4 - Digital input. | |||
* 5 - Open Drain output 10MHz. | |||
* 6 - Open Drain output 2MHz. | |||
* 7 - Open Drain output 50MHz. | |||
* 8 - Digital input with PullUp or PullDown resistor depending on ODR. | |||
* 9 - Alternate Push Pull output 10MHz. | |||
* A - Alternate Push Pull output 2MHz. | |||
* B - Alternate Push Pull output 50MHz. | |||
* C - Reserved. | |||
* D - Alternate Open Drain output 10MHz. | |||
* E - Alternate Open Drain output 2MHz. | |||
* F - Alternate Open Drain output 50MHz. | |||
* Please refer to the STM32 Reference Manual for details. | |||
*/ | |||
/* | |||
* Port A setup. | |||
* Everything input with pull-up except: | |||
*/ | |||
#define VAL_GPIOACRL 0x88888888 /* PA7...PA0 */ | |||
#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */ | |||
#define VAL_GPIOAODR 0xFFFFFFFF | |||
/* | |||
* Port B setup. | |||
* Everything input with pull-up except: | |||
*/ | |||
#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */ | |||
#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */ | |||
#define VAL_GPIOBODR 0xFFFFFFFF | |||
/* | |||
* Port C setup. | |||
* Everything input with pull-up except: | |||
*/ | |||
#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */ | |||
#define VAL_GPIOCCRH 0x88888888 /* PC15...PC8 */ | |||
#define VAL_GPIOCODR 0xFFFFFFFF | |||
/* | |||
* Port D setup. | |||
* Everything input with pull-up except: | |||
* PD0 - Normal input (XTAL). | |||
* PD1 - Normal input (XTAL). | |||
*/ | |||
#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */ | |||
#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ | |||
#define VAL_GPIODODR 0xFFFFFFFF | |||
/* | |||
* Port E setup. | |||
* Everything input with pull-up except: | |||
*/ | |||
#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ | |||
#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ | |||
#define VAL_GPIOEODR 0xFFFFFFFF | |||
/* | |||
* USB bus activation macro, required by the USB driver. | |||
*/ | |||
#define usb_lld_connect_bus(usbp) /* always connected */ | |||
/* | |||
* USB bus de-activation macro, required by the USB driver. | |||
*/ | |||
#define usb_lld_disconnect_bus(usbp) /* always connected */ | |||
#if !defined(_FROM_ASM_) | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
void boardInit(void); | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* _FROM_ASM_ */ | |||
#endif /* _BOARD_H_ */ |
@ -1,5 +0,0 @@ | |||
# List of all the board related files. | |||
BOARDSRC = $(BOARD_PATH)/boards/JM60_BOARD/board.c | |||
# Required include directories | |||
BOARDINC = $(BOARD_PATH)/boards/JM60_BOARD |
@ -1,266 +0,0 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
/* | |||
* This file has been automatically generated using ChibiStudio board | |||
* generator plugin. Do not edit manually. | |||
*/ | |||
#include <hal.h> | |||
#include <stm32_gpio.h> | |||
/*===========================================================================*/ | |||
/* Driver local definitions. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver exported variables. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver local variables and types. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Type of STM32 GPIO port setup. | |||
*/ | |||
typedef struct { | |||
uint32_t moder; | |||
uint32_t otyper; | |||
uint32_t ospeedr; | |||
uint32_t pupdr; | |||
uint32_t odr; | |||
uint32_t afrl; | |||
uint32_t afrh; | |||
} gpio_setup_t; | |||
/** | |||
* @brief Type of STM32 GPIO initialization data. | |||
*/ | |||
typedef struct { | |||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__) | |||
gpio_setup_t PAData; | |||
#endif | |||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__) | |||
gpio_setup_t PBData; | |||
#endif | |||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__) | |||
gpio_setup_t PCData; | |||
#endif | |||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__) | |||
gpio_setup_t PDData; | |||
#endif | |||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__) | |||
gpio_setup_t PEData; | |||
#endif | |||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__) | |||
gpio_setup_t PFData; | |||
#endif | |||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__) | |||
gpio_setup_t PGData; | |||
#endif | |||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__) | |||
gpio_setup_t PHData; | |||
#endif | |||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__) | |||
gpio_setup_t PIData; | |||
#endif | |||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) | |||
gpio_setup_t PJData; | |||
#endif | |||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__) | |||
gpio_setup_t PKData; | |||
#endif | |||
} gpio_config_t; | |||
/** | |||
* @brief STM32 GPIO static initialization data. | |||
*/ | |||
static const gpio_config_t gpio_default_config = { | |||
#if STM32_HAS_GPIOA | |||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, | |||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOB | |||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, | |||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOC | |||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, | |||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOD | |||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, | |||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOE | |||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, | |||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOF | |||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, | |||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOG | |||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, | |||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOH | |||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, | |||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOI | |||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, | |||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOJ | |||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, | |||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOK | |||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, | |||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} | |||
#endif | |||
}; | |||
/*===========================================================================*/ | |||
/* Driver local functions. */ | |||
/*===========================================================================*/ | |||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { | |||
gpiop->OTYPER = config->otyper; | |||
gpiop->OSPEEDR = config->ospeedr; | |||
gpiop->PUPDR = config->pupdr; | |||
gpiop->ODR = config->odr; | |||
gpiop->AFRL = config->afrl; | |||
gpiop->AFRH = config->afrh; | |||
gpiop->MODER = config->moder; | |||
} | |||
static void stm32_gpio_init(void) { | |||
/* Enabling GPIO-related clocks, the mask comes from the | |||
registry header file.*/ | |||
rccResetAHB1(STM32_GPIO_EN_MASK); | |||
rccEnableAHB1(STM32_GPIO_EN_MASK, true); | |||
/* Initializing all the defined GPIO ports.*/ | |||
#if STM32_HAS_GPIOA | |||
gpio_init(GPIOA, &gpio_default_config.PAData); | |||
#endif | |||
#if STM32_HAS_GPIOB | |||
gpio_init(GPIOB, &gpio_default_config.PBData); | |||
#endif | |||
#if STM32_HAS_GPIOC | |||
gpio_init(GPIOC, &gpio_default_config.PCData); | |||
#endif | |||
#if STM32_HAS_GPIOD | |||
gpio_init(GPIOD, &gpio_default_config.PDData); | |||
#endif | |||
#if STM32_HAS_GPIOE | |||
gpio_init(GPIOE, &gpio_default_config.PEData); | |||
#endif | |||
#if STM32_HAS_GPIOF | |||
gpio_init(GPIOF, &gpio_default_config.PFData); | |||
#endif | |||
#if STM32_HAS_GPIOG | |||
gpio_init(GPIOG, &gpio_default_config.PGData); | |||
#endif | |||
#if STM32_HAS_GPIOH | |||
gpio_init(GPIOH, &gpio_default_config.PHData); | |||
#endif | |||
#if STM32_HAS_GPIOI | |||
gpio_init(GPIOI, &gpio_default_config.PIData); | |||
#endif | |||
#if STM32_HAS_GPIOJ | |||
gpio_init(GPIOJ, &gpio_default_config.PJData); | |||
#endif | |||
#if STM32_HAS_GPIOK | |||
gpio_init(GPIOK, &gpio_default_config.PKData); | |||
#endif | |||
} | |||
/*===========================================================================*/ | |||
/* Driver interrupt handlers. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver exported functions. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Early initialization code. | |||
* @details GPIO ports and system clocks are initialized before everything | |||
* else. | |||
*/ | |||
void __early_init(void) { | |||
stm32_gpio_init(); | |||
stm32_clock_init(); | |||
} | |||
#if HAL_USE_SDC || defined(__DOXYGEN__) | |||
/** | |||
* @brief SDC card detection. | |||
*/ | |||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { | |||
(void)sdcp; | |||
/* TODO: Fill the implementation.*/ | |||
return true; | |||
} | |||
/** | |||
* @brief SDC card write protection detection. | |||
*/ | |||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) { | |||
(void)sdcp; | |||
/* TODO: Fill the implementation.*/ | |||
return false; | |||
} | |||
#endif /* HAL_USE_SDC */ | |||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) | |||
/** | |||
* @brief MMC_SPI card detection. | |||
*/ | |||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { | |||
(void)mmcp; | |||
/* TODO: Fill the implementation.*/ | |||
return true; | |||
} | |||
/** | |||
* @brief MMC_SPI card write protection detection. | |||
*/ | |||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) { | |||
(void)mmcp; | |||
/* TODO: Fill the implementation.*/ | |||
return false; | |||
} | |||
#endif | |||
/** | |||
* @brief Board-specific initialization code. | |||
* @todo Add your board-specific code, if any. | |||
*/ | |||
void boardInit(void) { | |||
} |
@ -1,9 +0,0 @@ | |||
# List of all the board related files. | |||
BOARDSRC = $(BOARD_PATH)/boards/m20add_bd/board.c | |||
# Required include directories | |||
BOARDINC = $(BOARD_PATH)/boards/m20add_bd | |||
# Shared variables | |||
ALLCSRC += $(BOARDSRC) | |||
ALLINC += $(BOARDINC) |
@ -1,266 +0,0 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
/* | |||
* This file has been automatically generated using ChibiStudio board | |||
* generator plugin. Do not edit manually. | |||
*/ | |||
#include <hal.h> | |||
#include <stm32_gpio.h> | |||
/*===========================================================================*/ | |||
/* Driver local definitions. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver exported variables. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver local variables and types. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Type of STM32 GPIO port setup. | |||
*/ | |||
typedef struct { | |||
uint32_t moder; | |||
uint32_t otyper; | |||
uint32_t ospeedr; | |||
uint32_t pupdr; | |||
uint32_t odr; | |||
uint32_t afrl; | |||
uint32_t afrh; | |||
} gpio_setup_t; | |||
/** | |||
* @brief Type of STM32 GPIO initialization data. | |||
*/ | |||
typedef struct { | |||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__) | |||
gpio_setup_t PAData; | |||
#endif | |||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__) | |||
gpio_setup_t PBData; | |||
#endif | |||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__) | |||
gpio_setup_t PCData; | |||
#endif | |||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__) | |||
gpio_setup_t PDData; | |||
#endif | |||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__) | |||
gpio_setup_t PEData; | |||
#endif | |||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__) | |||
gpio_setup_t PFData; | |||
#endif | |||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__) | |||
gpio_setup_t PGData; | |||
#endif | |||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__) | |||
gpio_setup_t PHData; | |||
#endif | |||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__) | |||
gpio_setup_t PIData; | |||
#endif | |||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) | |||
gpio_setup_t PJData; | |||
#endif | |||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__) | |||
gpio_setup_t PKData; | |||
#endif | |||
} gpio_config_t; | |||
/** | |||
* @brief STM32 GPIO static initialization data. | |||
*/ | |||
static const gpio_config_t gpio_default_config = { | |||
#if STM32_HAS_GPIOA | |||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, | |||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOB | |||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, | |||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOC | |||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, | |||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOD | |||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, | |||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOE | |||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, | |||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOF | |||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, | |||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOG | |||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, | |||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOH | |||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, | |||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOI | |||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, | |||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOJ | |||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, | |||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOK | |||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, | |||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} | |||
#endif | |||
}; | |||
/*===========================================================================*/ | |||
/* Driver local functions. */ | |||
/*===========================================================================*/ | |||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { | |||
gpiop->OTYPER = config->otyper; | |||
gpiop->OSPEEDR = config->ospeedr; | |||
gpiop->PUPDR = config->pupdr; | |||
gpiop->ODR = config->odr; | |||
gpiop->AFRL = config->afrl; | |||
gpiop->AFRH = config->afrh; | |||
gpiop->MODER = config->moder; | |||
} | |||
static void stm32_gpio_init(void) { | |||
/* Enabling GPIO-related clocks, the mask comes from the | |||
registry header file.*/ | |||
rccResetAHB1(STM32_GPIO_EN_MASK); | |||
rccEnableAHB1(STM32_GPIO_EN_MASK, true); | |||
/* Initializing all the defined GPIO ports.*/ | |||
#if STM32_HAS_GPIOA | |||
gpio_init(GPIOA, &gpio_default_config.PAData); | |||
#endif | |||
#if STM32_HAS_GPIOB | |||
gpio_init(GPIOB, &gpio_default_config.PBData); | |||
#endif | |||
#if STM32_HAS_GPIOC | |||
gpio_init(GPIOC, &gpio_default_config.PCData); | |||
#endif | |||
#if STM32_HAS_GPIOD | |||
gpio_init(GPIOD, &gpio_default_config.PDData); | |||
#endif | |||
#if STM32_HAS_GPIOE | |||
gpio_init(GPIOE, &gpio_default_config.PEData); | |||
#endif | |||
#if STM32_HAS_GPIOF | |||
gpio_init(GPIOF, &gpio_default_config.PFData); | |||
#endif | |||
#if STM32_HAS_GPIOG | |||
gpio_init(GPIOG, &gpio_default_config.PGData); | |||
#endif | |||
#if STM32_HAS_GPIOH | |||
gpio_init(GPIOH, &gpio_default_config.PHData); | |||
#endif | |||
#if STM32_HAS_GPIOI | |||
gpio_init(GPIOI, &gpio_default_config.PIData); | |||
#endif | |||
#if STM32_HAS_GPIOJ | |||
gpio_init(GPIOJ, &gpio_default_config.PJData); | |||
#endif | |||
#if STM32_HAS_GPIOK | |||
gpio_init(GPIOK, &gpio_default_config.PKData); | |||
#endif | |||
} | |||
/*===========================================================================*/ | |||
/* Driver interrupt handlers. */ | |||
/*===========================================================================*/ | |||
/*===========================================================================*/ | |||
/* Driver exported functions. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Early initialization code. | |||
* @details GPIO ports and system clocks are initialized before everything | |||
* else. | |||
*/ | |||
void __early_init(void) { | |||
stm32_gpio_init(); | |||
stm32_clock_init(); | |||
} | |||
#if HAL_USE_SDC || defined(__DOXYGEN__) | |||
/** | |||
* @brief SDC card detection. | |||
*/ | |||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { | |||
(void)sdcp; | |||
/* TODO: Fill the implementation.*/ | |||
return true; | |||
} | |||
/** | |||
* @brief SDC card write protection detection. | |||
*/ | |||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) { | |||
(void)sdcp; | |||
/* TODO: Fill the implementation.*/ | |||
return false; | |||
} | |||
#endif /* HAL_USE_SDC */ | |||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) | |||
/** | |||
* @brief MMC_SPI card detection. | |||
*/ | |||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { | |||
(void)mmcp; | |||
/* TODO: Fill the implementation.*/ | |||
return true; | |||
} | |||
/** | |||
* @brief MMC_SPI card write protection detection. | |||
*/ | |||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) { | |||
(void)mmcp; | |||
/* TODO: Fill the implementation.*/ | |||
return false; | |||
} | |||
#endif | |||
/** | |||
* @brief Board-specific initialization code. | |||
* @todo Add your board-specific code, if any. | |||
*/ | |||
void boardInit(void) { | |||
} |
@ -1,9 +0,0 @@ | |||
# List of all the board related files. | |||
BOARDSRC = $(BOARD_PATH)/boards/noah_bd/board.c | |||
# Required include directories | |||
BOARDINC = $(BOARD_PATH)/boards/noah_bd | |||
# Shared variables | |||
ALLCSRC += $(BOARDSRC) | |||
ALLINC += $(BOARDINC) |