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/* |
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio |
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Licensed under the Apache License, Version 2.0 (the "License"); |
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you may not use this file except in compliance with the License. |
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You may obtain a copy of the License at |
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http://www.apache.org/licenses/LICENSE-2.0 |
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Unless required by applicable law or agreed to in writing, software |
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distributed under the License is distributed on an "AS IS" BASIS, |
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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See the License for the specific language governing permissions and |
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limitations under the License. |
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*/ |
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/* |
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* STM32WB55xx drivers configuration. |
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* The following settings override the default settings present in |
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* the various device driver implementation headers. |
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* Note that the settings for each driver only have effect if the whole |
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* driver is enabled in halconf.h. |
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* |
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* IRQ priorities: |
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* 15...0 Lowest...Highest. |
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* |
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* DMA priorities: |
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* 0...3 Lowest...Highest. |
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*/ |
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#ifndef MCUCONF_H |
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#define MCUCONF_H |
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#define STM32WBxx_MCUCONF |
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#define STM32WB55_MCUCONF |
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/* |
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* HAL driver system settings. |
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*/ |
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#define STM32_NO_INIT FALSE |
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#define STM32_VOS STM32_VOS_RANGE1 |
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#define STM32_PVD_ENABLE FALSE |
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#define STM32_PLS STM32_PLS_LEV0 |
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#define STM32_HSI16_ENABLED TRUE |
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#define STM32_HSI48_ENABLED FALSE |
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#define STM32_LSI1_ENABLED TRUE |
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#define STM32_LSI2_ENABLED FALSE |
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#define STM32_HSE32_ENABLED TRUE |
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#define STM32_LSE_ENABLED TRUE |
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#define STM32_MSIPLL_ENABLED TRUE |
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#define STM32_MSIRANGE STM32_MSIRANGE_4M |
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#define STM32_SW STM32_SW_HSE |
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#define STM32_PLLSRC STM32_PLLSRC_MSI |
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#define STM32_PLLM_VALUE 1 |
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#define STM32_PLLN_VALUE 32 |
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#define STM32_PLLP_VALUE 2 |
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#define STM32_PLLQ_VALUE 2 |
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#define STM32_PLLR_VALUE 2 |
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#define STM32_HPRE STM32_HPRE_DIV1 |
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#define STM32_PPRE1 STM32_PPRE1_DIV1 |
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#define STM32_PPRE2 STM32_PPRE2_DIV1 |
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#define STM32_C2HPRE STM32_C2HPRE_DIV2 |
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#define STM32_SHDHPRE STM32_SHDHPRE_DIV1 |
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#define STM32_STOPWUCK STM32_STOPWUCK_MSI |
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK |
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#define STM32_MCOPRE STM32_MCOPRE_DIV1 |
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK |
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#define STM32_PLLSAI1N_VALUE 24 |
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#define STM32_PLLSAI1P_VALUE 2 |
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#define STM32_PLLSAI1Q_VALUE 2 |
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#define STM32_PLLSAI1R_VALUE 2 |
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/* |
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* Peripherals clock sources. |
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*/ |
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#define STM32_USART1SEL STM32_USART1SEL_PCLK2 |
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#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1 |
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 |
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#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 |
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 |
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 |
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#define STM32_SAI1SEL STM32_SAI1SEL_OFF |
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK |
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK |
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#define STM32_RTCSEL STM32_RTCSEL_LSI |
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/* |
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* IRQ system settings. |
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*/ |
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#define STM32_IRQ_EXTI0_PRIORITY 6 |
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#define STM32_IRQ_EXTI1_PRIORITY 6 |
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#define STM32_IRQ_EXTI2_PRIORITY 6 |
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#define STM32_IRQ_EXTI3_PRIORITY 6 |
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#define STM32_IRQ_EXTI4_PRIORITY 6 |
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#define STM32_IRQ_EXTI5_9_PRIORITY 6 |
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#define STM32_IRQ_EXTI10_15_PRIORITY 6 |
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#define STM32_IRQ_EXTI16_31_33_PRIORITY 6 |
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#define STM32_IRQ_EXTI17_PRIORITY 6 |
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#define STM32_IRQ_EXTI18_PRIORITY 6 |
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#define STM32_IRQ_EXTI19_PRIORITY 6 |
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#define STM32_IRQ_EXTI20_21_PRIORITY 6 |
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#define STM32_IRQ_TIM1_BRK_PRIORITY 7 |
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#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 |
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#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 |
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#define STM32_IRQ_TIM1_CC_PRIORITY 7 |
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#define STM32_IRQ_TIM2_PRIORITY 7 |
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#define STM32_IRQ_TIM16_PRIORITY 7 |
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#define STM32_IRQ_TIM17_PRIORITY 7 |
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#define STM32_IRQ_USART1_PRIORITY 3 |
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#define STM32_IRQ_LPUART1_PRIORITY 3 |
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/* |
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* ADC driver system settings. |
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*/ |
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#define STM32_ADC_COMPACT_SAMPLES FALSE |
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#define STM32_ADC_USE_ADC1 FALSE |
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_ADC_ADC1_DMA_PRIORITY 2 |
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#define STM32_ADC_ADC1_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
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#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2 |
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/* |
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* GPT driver system settings. |
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*/ |
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#define STM32_GPT_USE_TIM1 FALSE |
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#define STM32_GPT_USE_TIM2 FALSE |
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#define STM32_GPT_USE_TIM16 FALSE |
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#define STM32_GPT_USE_TIM17 FALSE |
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/* |
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* I2C driver system settings. |
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*/ |
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#define STM32_I2C_USE_I2C1 FALSE |
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#define STM32_I2C_USE_I2C3 FALSE |
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#define STM32_I2C_BUSY_TIMEOUT 50 |
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5 |
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5 |
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#define STM32_I2C_I2C1_DMA_PRIORITY 3 |
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#define STM32_I2C_I2C3_DMA_PRIORITY 3 |
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") |
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/* |
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* ICU driver system settings. |
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*/ |
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#define STM32_ICU_USE_TIM1 FALSE |
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#define STM32_ICU_USE_TIM2 FALSE |
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/* |
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* PWM driver system settings. |
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*/ |
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#define STM32_PWM_USE_TIM1 FALSE |
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#define STM32_PWM_USE_TIM2 FALSE |
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#define STM32_PWM_USE_TIM16 FALSE |
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#define STM32_PWM_USE_TIM17 FALSE |
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/* |
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* RTC driver system settings. |
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*/ |
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#define STM32_RTC_PRESA_VALUE 32 |
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#define STM32_RTC_PRESS_VALUE 1024 |
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#define STM32_RTC_CR_INIT 0 |
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#define STM32_RTC_TAMPCR_INIT 0 |
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/* |
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* SERIAL driver system settings. |
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*/ |
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#define STM32_SERIAL_USE_USART1 TRUE |
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#define STM32_SERIAL_USE_LPUART1 FALSE |
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#define STM32_SERIAL_USART1_PRIORITY 12 |
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#define STM32_SERIAL_LPUART1_PRIORITY 12 |
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/* |
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* SIO driver system settings. |
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*/ |
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#define STM32_SIO_USE_USART1 FALSE |
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#define STM32_SIO_USE_LPUART1 FALSE |
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/* |
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* SPI driver system settings. |
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*/ |
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#define STM32_SPI_USE_SPI1 TRUE |
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#define STM32_SPI_USE_SPI2 FALSE |
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_SPI_SPI1_DMA_PRIORITY 1 |
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#define STM32_SPI_SPI2_DMA_PRIORITY 1 |
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10 |
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
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/* |
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* ST driver system settings. |
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*/ |
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#define STM32_ST_IRQ_PRIORITY 8 |
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#define STM32_ST_USE_TIMER 2 |
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/* |
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* TRNG driver system settings. |
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*/ |
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#define STM32_TRNG_USE_RNG1 FALSE |
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/* |
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* UART driver system settings. |
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*/ |
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#define STM32_UART_USE_USART1 FALSE |
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_UART_USART1_IRQ_PRIORITY 12 |
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#define STM32_UART_USART1_DMA_PRIORITY 0 |
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") |
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/* |
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* USB driver system settings. |
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*/ |
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#define STM32_USB_USE_USB1 TRUE |
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#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE |
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#define STM32_USB_USB1_HP_IRQ_PRIORITY 12 |
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#define STM32_USB_USB1_LP_IRQ_PRIORITY 12 |
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/* |
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* WDG driver system settings. |
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*/ |
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#define STM32_WDG_USE_IWDG FALSE |
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/* |
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* WSPI driver system settings. |
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*/ |
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#define STM32_WSPI_USE_QUADSPI1 FALSE |
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 |
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#endif /* MCUCONF_H */ |