* added ixora files * upload ixora * update readme * Update keyboards/peiorisboards/ixora/ixora.h Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/ixora.h Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/ixora.h Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/keymaps/default/keymap.c Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/keymaps/default/keymap.c Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/keymaps/wntrmln/keymap.c Co-Authored-By: fauxpark <fauxpark@gmail.com> * Update keyboards/peiorisboards/ixora/keymaps/wntrmln/keymap.c Co-Authored-By: fauxpark <fauxpark@gmail.com> * update files according to suggestions * removed unused codepull/5951/head
@ -0,0 +1,101 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
#include "hal.h" | |||
#if HAL_USE_PAL || defined(__DOXYGEN__) | |||
/** | |||
* @brief PAL setup. | |||
* @details Digital I/O ports static configuration as defined in @p board.h. | |||
* This variable is used by the HAL when initializing the PAL driver. | |||
*/ | |||
const PALConfig pal_default_config = { | |||
#if STM32_HAS_GPIOA | |||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, | |||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOB | |||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, | |||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOC | |||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, | |||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOD | |||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, | |||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOE | |||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, | |||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOF | |||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, | |||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOG | |||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, | |||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOH | |||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, | |||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, | |||
#endif | |||
#if STM32_HAS_GPIOI | |||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, | |||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} | |||
#endif | |||
}; | |||
#endif | |||
void enter_bootloader_mode_if_requested(void); | |||
/** | |||
* @brief Early initialization code. | |||
* @details This initialization must be performed just after stack setup | |||
* and before any other initialization. | |||
*/ | |||
void __early_init(void) { | |||
enter_bootloader_mode_if_requested(); | |||
stm32_clock_init(); | |||
} | |||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) | |||
/** | |||
* @brief MMC_SPI card detection. | |||
*/ | |||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { | |||
(void)mmcp; | |||
/* TODO: Fill the implementation.*/ | |||
return true; | |||
} | |||
/** | |||
* @brief MMC_SPI card write protection detection. | |||
*/ | |||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) { | |||
(void)mmcp; | |||
/* TODO: Fill the implementation.*/ | |||
return false; | |||
} | |||
#endif | |||
/** | |||
* @brief Board-specific initialization code. | |||
* @todo Add your board-specific code, if any. | |||
*/ | |||
void boardInit(void) { | |||
} |
@ -0,0 +1,896 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
#ifndef _BOARD_H | |||
#define _BOARD_H | |||
/* | |||
* Setup for STMicroelectronics STM32 Nucleo32-F042K6 board. | |||
*/ | |||
/* | |||
* Board identifier. | |||
*/ | |||
#define BOARD_GENERIC_STM32_F042X6 | |||
#define BOARD_NAME "Generic STM32F042 PCB" | |||
/* | |||
* Board oscillators-related settings. | |||
* NOTE: LSE not fitted. | |||
* NOTE: HSE not fitted. | |||
*/ | |||
#if !defined(STM32_LSECLK) | |||
#define STM32_LSECLK 0U | |||
#endif | |||
#define STM32_LSEDRV (3U << 3U) | |||
#if !defined(STM32_HSECLK) | |||
#define STM32_HSECLK 0U | |||
#endif | |||
/* | |||
* MCU type as defined in the ST header. | |||
*/ | |||
#define STM32F042x6 | |||
/* | |||
* IO pins assignments. | |||
*/ | |||
#define GPIOA_PIN0 0U | |||
#define GPIOA_PIN1 1U | |||
#define GPIOA_PIN2 2U | |||
#define GPIOA_PIN3 3U | |||
#define GPIOA_PIN4 4U | |||
#define GPIOA_PIN5 5U | |||
#define GPIOA_PIN6 6U | |||
#define GPIOA_PIN7 7U | |||
#define GPIOA_PIN8 8U | |||
#define GPIOA_PIN9 9U | |||
#define GPIOA_PIN10 10U | |||
#define GPIOA_PIN11 11U | |||
#define GPIOA_PIN12 12U | |||
#define GPIOA_PIN13 13U | |||
#define GPIOA_PIN14 14U | |||
#define GPIOA_PIN15 15U | |||
#define GPIOB_PIN0 0U | |||
#define GPIOB_PIN1 1U | |||
#define GPIOB_PIN2 2U | |||
#define GPIOB_PIN3 3U | |||
#define GPIOB_PIN4 4U | |||
#define GPIOB_PIN5 5U | |||
#define GPIOB_PIN6 6U | |||
#define GPIOB_PIN7 7U | |||
#define GPIOB_PIN8 8U | |||
#define GPIOB_PIN9 9U | |||
#define GPIOB_PIN10 10U | |||
#define GPIOB_PIN11 11U | |||
#define GPIOB_PIN12 12U | |||
#define GPIOB_PIN13 13U | |||
#define GPIOB_PIN14 14U | |||
#define GPIOB_PIN15 15U | |||
#define GPIOC_PIN0 0U | |||
#define GPIOC_PIN1 1U | |||
#define GPIOC_PIN2 2U | |||
#define GPIOC_PIN3 3U | |||
#define GPIOC_PIN4 4U | |||
#define GPIOC_PIN5 5U | |||
#define GPIOC_PIN6 6U | |||
#define GPIOC_PIN7 7U | |||
#define GPIOC_PIN8 8U | |||
#define GPIOC_PIN9 9U | |||
#define GPIOC_PIN10 10U | |||
#define GPIOC_PIN11 11U | |||
#define GPIOC_PIN12 12U | |||
#define GPIOC_PIN13 13U | |||
#define GPIOC_PIN14 14U | |||
#define GPIOC_PIN15 15U | |||
#define GPIOD_PIN0 0U | |||
#define GPIOD_PIN1 1U | |||
#define GPIOD_PIN2 2U | |||
#define GPIOD_PIN3 3U | |||
#define GPIOD_PIN4 4U | |||
#define GPIOD_PIN5 5U | |||
#define GPIOD_PIN6 6U | |||
#define GPIOD_PIN7 7U | |||
#define GPIOD_PIN8 8U | |||
#define GPIOD_PIN9 9U | |||
#define GPIOD_PIN10 10U | |||
#define GPIOD_PIN11 11U | |||
#define GPIOD_PIN12 12U | |||
#define GPIOD_PIN13 13U | |||
#define GPIOD_PIN14 14U | |||
#define GPIOD_PIN15 15U | |||
#define GPIOE_PIN0 0U | |||
#define GPIOE_PIN1 1U | |||
#define GPIOE_PIN2 2U | |||
#define GPIOE_PIN3 3U | |||
#define GPIOE_PIN4 4U | |||
#define GPIOE_PIN5 5U | |||
#define GPIOE_PIN6 6U | |||
#define GPIOE_PIN7 7U | |||
#define GPIOE_PIN8 8U | |||
#define GPIOE_PIN9 9U | |||
#define GPIOE_PIN10 10U | |||
#define GPIOE_PIN11 11U | |||
#define GPIOE_PIN12 12U | |||
#define GPIOE_PIN13 13U | |||
#define GPIOE_PIN14 14U | |||
#define GPIOE_PIN15 15U | |||
#define GPIOF_PIN0 0U | |||
#define GPIOF_PIN1 1U | |||
#define GPIOF_PIN2 2U | |||
#define GPIOF_PIN3 3U | |||
#define GPIOF_PIN4 4U | |||
#define GPIOF_PIN5 5U | |||
#define GPIOF_PIN6 6U | |||
#define GPIOF_PIN7 7U | |||
#define GPIOF_PIN8 8U | |||
#define GPIOF_PIN9 9U | |||
#define GPIOF_PIN10 10U | |||
#define GPIOF_PIN11 11U | |||
#define GPIOF_PIN12 12U | |||
#define GPIOF_PIN13 13U | |||
#define GPIOF_PIN14 14U | |||
#define GPIOF_PIN15 15U | |||
/* | |||
* IO lines assignments. | |||
*/ | |||
#define LINE_BOOT0 PAL_LINE(GPIOB, 8U) | |||
#define LINE_SWCLK PAL_LINE(GPIOA, 14U) | |||
#define LINE_SWDIO PAL_LINE(GPIOA, 13U) | |||
/* | |||
* I/O ports initial setup, this configuration is established soon after reset | |||
* in the initialization code. | |||
* Please refer to the STM32 Reference Manual for details. | |||
*/ | |||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) | |||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) | |||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) | |||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) | |||
#define PIN_ODR_LOW(n) (0U << (n)) | |||
#define PIN_ODR_HIGH(n) (1U << (n)) | |||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) | |||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) | |||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) | |||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) | |||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) | |||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) | |||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) | |||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) | |||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) | |||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) | |||
/* | |||
* GPIOA setup: | |||
* | |||
* PA0 - COL5 | |||
* PA1 - COL4 | |||
* PA2 - COL3 | |||
* PA3 - COL2 | |||
* PA4 - COL1 | |||
* PA5 - COL0 | |||
* PA6 - ROW4 | |||
* PA7 - ROW3 | |||
* PA8 - NC | |||
* PA9 - ROW1 | |||
* PA10 - ROW0 | |||
* PA11 - USB_DM | |||
* PA12 - USB_DP | |||
* PA13 - COL15/SWDIO (for now, COL15) | |||
* PA14 - COL14/SWCLK (for now, COL14) | |||
* PA15 - COL13 | |||
*/ | |||
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN1) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN2) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN3) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN4) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN5) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN6) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN7) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOA_PIN15)) | |||
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) | |||
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN2) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN7) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN8) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN9) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOA_PIN11) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN12) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN13) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN14) | \ | |||
PIN_OSPEED_VERYLOW(GPIOA_PIN15)) | |||
#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN7) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN10) | \ | |||
PIN_PUPDR_FLOATING(GPIOA_PIN11) | \ | |||
PIN_PUPDR_FLOATING(GPIOA_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOA_PIN15)) | |||
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN1) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN2) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN3) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN4) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN5) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN6) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN7) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOA_PIN15)) | |||
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN7, 0U)) | |||
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOA_PIN15, 0U)) | |||
/* | |||
* GPIOB setup: | |||
* | |||
* PB0 - ROW2 | |||
* PB1 - RGB_D | |||
* PB2 - PIN2 (input pullup). | |||
* PB3 - COL12 | |||
* PB4 - COL11 | |||
* PB5 - COL10 | |||
* PB6 - COL9 | |||
* PB7 - COL8 | |||
* PB8 - BOOT0 (set as output for STM32F042) | |||
* PB9 - PIN9 (input pullup). | |||
* PB10 - PIN10 (input pullup). | |||
* PB11 - PIN11 (input pullup). | |||
* PB12 - PIN12 (input pullup). | |||
* PB13 - PIN13 (input pullup). | |||
* PB14 - PIN14 (input pullup). | |||
* PB15 - PIN15 (input pullup). | |||
*/ | |||
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ | |||
PIN_MODE_OUTPUT(GPIOB_PIN1) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN2) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN3) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN4) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN5) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN6) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN7) | \ | |||
PIN_MODE_OUTPUT(GPIOB_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOB_PIN15)) | |||
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) | |||
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN1) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN2) | \ | |||
PIN_OSPEED_VERYLOW(GPIOB_PIN3) | \ | |||
PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \ | |||
PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \ | |||
PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \ | |||
PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \ | |||
PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN9) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN11) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN12) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN13) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN14) | \ | |||
PIN_OSPEED_HIGH(GPIOB_PIN15)) | |||
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ | |||
PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN3) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ | |||
PIN_PUPDR_PULLDOWN(GPIOB_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOB_PIN15)) | |||
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN1) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN2) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN3) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN4) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN5) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN6) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN7) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOB_PIN15)) | |||
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN7, 0U)) | |||
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOB_PIN15, 0U)) | |||
/* | |||
* GPIOC setup: | |||
* | |||
* PC0 - PIN0 (input pullup). | |||
* PC1 - PIN1 (input pullup). | |||
* PC2 - PIN2 (input pullup). | |||
* PC3 - PIN3 (input pullup). | |||
* PC4 - PIN4 (input pullup). | |||
* PC5 - PIN5 (input pullup). | |||
* PC6 - PIN6 (input pullup). | |||
* PC7 - PIN7 (input pullup). | |||
* PC8 - PIN8 (input pullup). | |||
* PC9 - PIN9 (input pullup). | |||
* PC10 - PIN10 (input pullup). | |||
* PC11 - PIN11 (input pullup). | |||
* PC12 - PIN12 (input pullup). | |||
* PC13 - PIN13 (input pullup). | |||
* PC14 - PIN14 (input pullup). | |||
* PC15 - PIN15 (input pullup). | |||
*/ | |||
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN1) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN2) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN3) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN4) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN5) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN6) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN7) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOC_PIN15)) | |||
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) | |||
#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN1) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN2) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN3) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN4) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN5) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN6) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN7) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN8) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN9) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN11) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN12) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN13) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN14) | \ | |||
PIN_OSPEED_HIGH(GPIOC_PIN15)) | |||
#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOC_PIN15)) | |||
#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN1) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN2) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN3) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN4) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN5) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN6) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN7) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOC_PIN15)) | |||
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN7, 0U)) | |||
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOC_PIN15, 0U)) | |||
/* | |||
* GPIOD setup: | |||
* | |||
* PD0 - PIN0 (input pullup). | |||
* PD1 - PIN1 (input pullup). | |||
* PD2 - PIN2 (input pullup). | |||
* PD3 - PIN3 (input pullup). | |||
* PD4 - PIN4 (input pullup). | |||
* PD5 - PIN5 (input pullup). | |||
* PD6 - PIN6 (input pullup). | |||
* PD7 - PIN7 (input pullup). | |||
* PD8 - PIN8 (input pullup). | |||
* PD9 - PIN9 (input pullup). | |||
* PD10 - PIN10 (input pullup). | |||
* PD11 - PIN11 (input pullup). | |||
* PD12 - PIN12 (input pullup). | |||
* PD13 - PIN13 (input pullup). | |||
* PD14 - PIN14 (input pullup). | |||
* PD15 - PIN15 (input pullup). | |||
*/ | |||
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN1) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN2) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN3) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN4) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN5) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN6) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN7) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOD_PIN15)) | |||
#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) | |||
#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN1) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN2) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN3) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN4) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN5) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN6) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN7) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN8) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN9) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN11) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN12) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN13) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN14) | \ | |||
PIN_OSPEED_HIGH(GPIOD_PIN15)) | |||
#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOD_PIN15)) | |||
#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN1) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN2) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN3) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN4) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN5) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN6) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN7) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOD_PIN15)) | |||
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN7, 0U)) | |||
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOD_PIN15, 0U)) | |||
/* | |||
* GPIOE setup: | |||
* | |||
* PE0 - PIN0 (input pullup). | |||
* PE1 - PIN1 (input pullup). | |||
* PE2 - PIN2 (input pullup). | |||
* PE3 - PIN3 (input pullup). | |||
* PE4 - PIN4 (input pullup). | |||
* PE5 - PIN5 (input pullup). | |||
* PE6 - PIN6 (input pullup). | |||
* PE7 - PIN7 (input pullup). | |||
* PE8 - PIN8 (input pullup). | |||
* PE9 - PIN9 (input pullup). | |||
* PE10 - PIN10 (input pullup). | |||
* PE11 - PIN11 (input pullup). | |||
* PE12 - PIN12 (input pullup). | |||
* PE13 - PIN13 (input pullup). | |||
* PE14 - PIN14 (input pullup). | |||
* PE15 - PIN15 (input pullup). | |||
*/ | |||
#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN1) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN2) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN3) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN4) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN5) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN6) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN7) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOE_PIN15)) | |||
#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) | |||
#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN1) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN2) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN3) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN4) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN5) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN6) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN7) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN8) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN9) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN11) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN12) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN13) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN14) | \ | |||
PIN_OSPEED_HIGH(GPIOE_PIN15)) | |||
#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOE_PIN15)) | |||
#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN1) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN2) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN3) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN4) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN5) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN6) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN7) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOE_PIN15)) | |||
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN7, 0U)) | |||
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOE_PIN15, 0U)) | |||
/* | |||
* GPIOF setup: | |||
* | |||
* PF0 - COL7 | |||
* PF1 - COL6 | |||
* PF2 - PIN2 (input pullup). | |||
* PF3 - PIN3 (input pullup). | |||
* PF4 - PIN4 (input pullup). | |||
* PF5 - PIN5 (input pullup). | |||
* PF6 - PIN6 (input pullup). | |||
* PF7 - PIN7 (input pullup). | |||
* PF8 - PIN8 (input pullup). | |||
* PF9 - PIN9 (input pullup). | |||
* PF10 - PIN10 (input pullup). | |||
* PF11 - PIN11 (input pullup). | |||
* PF12 - PIN12 (input pullup). | |||
* PF13 - PIN13 (input pullup). | |||
* PF14 - PIN14 (input pullup). | |||
* PF15 - PIN15 (input pullup). | |||
*/ | |||
#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN1) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN2) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN3) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN4) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN5) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN6) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN7) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN8) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN9) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN10) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN11) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN12) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN13) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN14) | \ | |||
PIN_MODE_INPUT(GPIOF_PIN15)) | |||
#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ | |||
PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) | |||
#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \ | |||
PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN2) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN3) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN4) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN5) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN6) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN7) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN8) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN9) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN10) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN11) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN12) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN13) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN14) | \ | |||
PIN_OSPEED_HIGH(GPIOF_PIN15)) | |||
#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ | |||
PIN_PUPDR_PULLUP(GPIOF_PIN15)) | |||
#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN1) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN2) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN3) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN4) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN5) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN6) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN7) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN8) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN9) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN10) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN11) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN12) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN13) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN14) | \ | |||
PIN_ODR_HIGH(GPIOF_PIN15)) | |||
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN7, 0U)) | |||
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ | |||
PIN_AFIO_AF(GPIOF_PIN15, 0U)) | |||
#if !defined(_FROM_ASM_) | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
void boardInit(void); | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* _FROM_ASM_ */ | |||
#endif /* _BOARD_H */ |
@ -0,0 +1,5 @@ | |||
# List of all the board related files. | |||
BOARDSRC = $(BOARD_PATH)/boards/GENERIC_STM32_F042X6/board.c | |||
# Required include directories | |||
BOARDINC = $(BOARD_PATH)/boards/GENERIC_STM32_F042X6 |
@ -0,0 +1,7 @@ | |||
/* Address for jumping to bootloader on STM32 chips. */ | |||
/* It is chip dependent, the correct number can be looked up here: | |||
* http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf | |||
* This also requires a patch to chibios: | |||
* <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch | |||
*/ | |||
#define STM32_BOOTLOADER_ADDRESS 0x1FFFC400 |
@ -0,0 +1,521 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
/** | |||
* @file templates/chconf.h | |||
* @brief Configuration file template. | |||
* @details A copy of this file must be placed in each project directory, it | |||
* contains the application specific kernel settings. | |||
* | |||
* @addtogroup config | |||
* @details Kernel related settings and hooks. | |||
* @{ | |||
*/ | |||
#ifndef CHCONF_H | |||
#define CHCONF_H | |||
#define _CHIBIOS_RT_CONF_ | |||
/*===========================================================================*/ | |||
/** | |||
* @name System timers settings | |||
* @{ | |||
*/ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief System time counter resolution. | |||
* @note Allowed values are 16 or 32 bits. | |||
*/ | |||
#define CH_CFG_ST_RESOLUTION 32 | |||
/** | |||
* @brief System tick frequency. | |||
* @details Frequency of the system timer that drives the system ticks. This | |||
* setting also defines the system tick time unit. | |||
*/ | |||
#define CH_CFG_ST_FREQUENCY 10000 | |||
/** | |||
* @brief Time delta constant for the tick-less mode. | |||
* @note If this value is zero then the system uses the classic | |||
* periodic tick. This value represents the minimum number | |||
* of ticks that is safe to specify in a timeout directive. | |||
* The value one is not valid, timeouts are rounded up to | |||
* this value. | |||
*/ | |||
#define CH_CFG_ST_TIMEDELTA 2 | |||
/** @} */ | |||
/*===========================================================================*/ | |||
/** | |||
* @name Kernel parameters and options | |||
* @{ | |||
*/ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Round robin interval. | |||
* @details This constant is the number of system ticks allowed for the | |||
* threads before preemption occurs. Setting this value to zero | |||
* disables the preemption for threads with equal priority and the | |||
* round robin becomes cooperative. Note that higher priority | |||
* threads can still preempt, the kernel is always preemptive. | |||
* @note Disabling the round robin preemption makes the kernel more compact | |||
* and generally faster. | |||
* @note The round robin preemption is not supported in tickless mode and | |||
* must be set to zero in that case. | |||
*/ | |||
#define CH_CFG_TIME_QUANTUM 0 | |||
/** | |||
* @brief Managed RAM size. | |||
* @details Size of the RAM area to be managed by the OS. If set to zero | |||
* then the whole available RAM is used. The core memory is made | |||
* available to the heap allocator and/or can be used directly through | |||
* the simplified core memory allocator. | |||
* | |||
* @note In order to let the OS manage the whole RAM the linker script must | |||
* provide the @p __heap_base__ and @p __heap_end__ symbols. | |||
* @note Requires @p CH_CFG_USE_MEMCORE. | |||
*/ | |||
#define CH_CFG_MEMCORE_SIZE 0 | |||
/** | |||
* @brief Idle thread automatic spawn suppression. | |||
* @details When this option is activated the function @p chSysInit() | |||
* does not spawn the idle thread. The application @p main() | |||
* function becomes the idle thread and must implement an | |||
* infinite loop. | |||
*/ | |||
#define CH_CFG_NO_IDLE_THREAD FALSE | |||
/* Use __WFI in the idle thread for waiting. Does lower the power | |||
* consumption. */ | |||
#define CORTEX_ENABLE_WFI_IDLE TRUE | |||
/** @} */ | |||
/*===========================================================================*/ | |||
/** | |||
* @name Performance options | |||
* @{ | |||
*/ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief OS optimization. | |||
* @details If enabled then time efficient rather than space efficient code | |||
* is used when two possible implementations exist. | |||
* | |||
* @note This is not related to the compiler optimization options. | |||
* @note The default is @p TRUE. | |||
*/ | |||
#define CH_CFG_OPTIMIZE_SPEED TRUE | |||
/** @} */ | |||
/*===========================================================================*/ | |||
/** | |||
* @name Subsystem options | |||
* @{ | |||
*/ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Time Measurement APIs. | |||
* @details If enabled then the time measurement APIs are included in | |||
* the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
*/ | |||
#define CH_CFG_USE_TM FALSE | |||
/** | |||
* @brief Threads registry APIs. | |||
* @details If enabled then the registry APIs are included in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
*/ | |||
#define CH_CFG_USE_REGISTRY TRUE | |||
/** | |||
* @brief Threads synchronization APIs. | |||
* @details If enabled then the @p chThdWait() function is included in | |||
* the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
*/ | |||
#define CH_CFG_USE_WAITEXIT TRUE | |||
/** | |||
* @brief Semaphores APIs. | |||
* @details If enabled then the Semaphores APIs are included in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
*/ | |||
#define CH_CFG_USE_SEMAPHORES TRUE | |||
/** | |||
* @brief Semaphores queuing mode. | |||
* @details If enabled then the threads are enqueued on semaphores by | |||
* priority rather than in FIFO order. | |||
* | |||
* @note The default is @p FALSE. Enable this if you have special | |||
* requirements. | |||
* @note Requires @p CH_CFG_USE_SEMAPHORES. | |||
*/ | |||
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE | |||
/** | |||
* @brief Mutexes APIs. | |||
* @details If enabled then the mutexes APIs are included in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
*/ | |||
#define CH_CFG_USE_MUTEXES TRUE | |||
/** | |||
* @brief Enables recursive behavior on mutexes. | |||
* @note Recursive mutexes are heavier and have an increased | |||
* memory footprint. | |||
* | |||
* @note The default is @p FALSE. | |||
* @note Requires @p CH_CFG_USE_MUTEXES. | |||
*/ | |||
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE | |||
/** | |||
* @brief Conditional Variables APIs. | |||
* @details If enabled then the conditional variables APIs are included | |||
* in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
* @note Requires @p CH_CFG_USE_MUTEXES. | |||
*/ | |||
#define CH_CFG_USE_CONDVARS TRUE | |||
/** | |||
* @brief Conditional Variables APIs with timeout. | |||
* @details If enabled then the conditional variables APIs with timeout | |||
* specification are included in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
* @note Requires @p CH_CFG_USE_CONDVARS. | |||
*/ | |||
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE | |||
/** | |||
* @brief Events Flags APIs. | |||
* @details If enabled then the event flags APIs are included in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
*/ | |||
#define CH_CFG_USE_EVENTS TRUE | |||
/** | |||
* @brief Events Flags APIs with timeout. | |||
* @details If enabled then the events APIs with timeout specification | |||
* are included in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
* @note Requires @p CH_CFG_USE_EVENTS. | |||
*/ | |||
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE | |||
/** | |||
* @brief Synchronous Messages APIs. | |||
* @details If enabled then the synchronous messages APIs are included | |||
* in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
*/ | |||
#define CH_CFG_USE_MESSAGES TRUE | |||
/** | |||
* @brief Synchronous Messages queuing mode. | |||
* @details If enabled then messages are served by priority rather than in | |||
* FIFO order. | |||
* | |||
* @note The default is @p FALSE. Enable this if you have special | |||
* requirements. | |||
* @note Requires @p CH_CFG_USE_MESSAGES. | |||
*/ | |||
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE | |||
/** | |||
* @brief Mailboxes APIs. | |||
* @details If enabled then the asynchronous messages (mailboxes) APIs are | |||
* included in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
* @note Requires @p CH_CFG_USE_SEMAPHORES. | |||
*/ | |||
#define CH_CFG_USE_MAILBOXES TRUE | |||
/** | |||
* @brief Core Memory Manager APIs. | |||
* @details If enabled then the core memory manager APIs are included | |||
* in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
*/ | |||
#define CH_CFG_USE_MEMCORE TRUE | |||
/** | |||
* @brief Heap Allocator APIs. | |||
* @details If enabled then the memory heap allocator APIs are included | |||
* in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or | |||
* @p CH_CFG_USE_SEMAPHORES. | |||
* @note Mutexes are recommended. | |||
*/ | |||
#define CH_CFG_USE_HEAP TRUE | |||
/** | |||
* @brief Memory Pools Allocator APIs. | |||
* @details If enabled then the memory pools allocator APIs are included | |||
* in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
*/ | |||
#define CH_CFG_USE_MEMPOOLS TRUE | |||
/** | |||
* @brief Dynamic Threads APIs. | |||
* @details If enabled then the dynamic threads creation APIs are included | |||
* in the kernel. | |||
* | |||
* @note The default is @p TRUE. | |||
* @note Requires @p CH_CFG_USE_WAITEXIT. | |||
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. | |||
*/ | |||
#define CH_CFG_USE_DYNAMIC TRUE | |||
/** @} */ | |||
/*===========================================================================*/ | |||
/** | |||
* @name Debug options | |||
* @{ | |||
*/ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Debug option, kernel statistics. | |||
* | |||
* @note The default is @p FALSE. | |||
*/ | |||
#define CH_DBG_STATISTICS FALSE | |||
/** | |||
* @brief Debug option, system state check. | |||
* @details If enabled the correct call protocol for system APIs is checked | |||
* at runtime. | |||
* | |||
* @note The default is @p FALSE. | |||
*/ | |||
#define CH_DBG_SYSTEM_STATE_CHECK FALSE | |||
/** | |||
* @brief Debug option, parameters checks. | |||
* @details If enabled then the checks on the API functions input | |||
* parameters are activated. | |||
* | |||
* @note The default is @p FALSE. | |||
*/ | |||
#define CH_DBG_ENABLE_CHECKS FALSE | |||
/** | |||
* @brief Debug option, consistency checks. | |||
* @details If enabled then all the assertions in the kernel code are | |||
* activated. This includes consistency checks inside the kernel, | |||
* runtime anomalies and port-defined checks. | |||
* | |||
* @note The default is @p FALSE. | |||
*/ | |||
#define CH_DBG_ENABLE_ASSERTS FALSE | |||
/** | |||
* @brief Debug option, trace buffer. | |||
* @details If enabled then the trace buffer is activated. | |||
* | |||
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED. | |||
*/ | |||
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED | |||
/** | |||
* @brief Trace buffer entries. | |||
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is | |||
* different from @p CH_DBG_TRACE_MASK_DISABLED. | |||
*/ | |||
#define CH_DBG_TRACE_BUFFER_SIZE 128 | |||
/** | |||
* @brief Debug option, stack checks. | |||
* @details If enabled then a runtime stack check is performed. | |||
* | |||
* @note The default is @p FALSE. | |||
* @note The stack check is performed in a architecture/port dependent way. | |||
* It may not be implemented or some ports. | |||
* @note The default failure mode is to halt the system with the global | |||
* @p panic_msg variable set to @p NULL. | |||
*/ | |||
#define CH_DBG_ENABLE_STACK_CHECK FALSE | |||
/** | |||
* @brief Debug option, stacks initialization. | |||
* @details If enabled then the threads working area is filled with a byte | |||
* value when a thread is created. This can be useful for the | |||
* runtime measurement of the used stack. | |||
* | |||
* @note The default is @p FALSE. | |||
*/ | |||
#define CH_DBG_FILL_THREADS FALSE | |||
/** | |||
* @brief Debug option, threads profiling. | |||
* @details If enabled then a field is added to the @p thread_t structure that | |||
* counts the system ticks occurred while executing the thread. | |||
* | |||
* @note The default is @p FALSE. | |||
* @note This debug option is not currently compatible with the | |||
* tickless mode. | |||
*/ | |||
#define CH_DBG_THREADS_PROFILING FALSE | |||
/** @} */ | |||
/*===========================================================================*/ | |||
/** | |||
* @name Kernel hooks | |||
* @{ | |||
*/ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Threads descriptor structure extension. | |||
* @details User fields added to the end of the @p thread_t structure. | |||
*/ | |||
#define CH_CFG_THREAD_EXTRA_FIELDS \ | |||
/* Add threads custom fields here.*/ | |||
/** | |||
* @brief Threads initialization hook. | |||
* @details User initialization code added to the @p chThdInit() API. | |||
* | |||
* @note It is invoked from within @p chThdInit() and implicitly from all | |||
* the threads creation APIs. | |||
*/ | |||
#define CH_CFG_THREAD_INIT_HOOK(tp) { \ | |||
/* Add threads initialization code here.*/ \ | |||
} | |||
/** | |||
* @brief Threads finalization hook. | |||
* @details User finalization code added to the @p chThdExit() API. | |||
*/ | |||
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ | |||
/* Add threads finalization code here.*/ \ | |||
} | |||
/** | |||
* @brief Context switch hook. | |||
* @details This hook is invoked just before switching between threads. | |||
*/ | |||
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ | |||
/* Context switch code here.*/ \ | |||
} | |||
/** | |||
* @brief ISR enter hook. | |||
*/ | |||
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ | |||
/* IRQ prologue code here.*/ \ | |||
} | |||
/** | |||
* @brief ISR exit hook. | |||
*/ | |||
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ | |||
/* IRQ epilogue code here.*/ \ | |||
} | |||
/** | |||
* @brief Idle thread enter hook. | |||
* @note This hook is invoked within a critical zone, no OS functions | |||
* should be invoked from here. | |||
* @note This macro can be used to activate a power saving mode. | |||
*/ | |||
#define CH_CFG_IDLE_ENTER_HOOK() { \ | |||
/* Idle-enter code here.*/ \ | |||
} | |||
/** | |||
* @brief Idle thread leave hook. | |||
* @note This hook is invoked within a critical zone, no OS functions | |||
* should be invoked from here. | |||
* @note This macro can be used to deactivate a power saving mode. | |||
*/ | |||
#define CH_CFG_IDLE_LEAVE_HOOK() { \ | |||
/* Idle-leave code here.*/ \ | |||
} | |||
/** | |||
* @brief Idle Loop hook. | |||
* @details This hook is continuously invoked by the idle thread loop. | |||
*/ | |||
#define CH_CFG_IDLE_LOOP_HOOK() { \ | |||
/* Idle loop code here.*/ \ | |||
} | |||
/** | |||
* @brief System tick event hook. | |||
* @details This hook is invoked in the system tick handler immediately | |||
* after processing the virtual timers queue. | |||
*/ | |||
#define CH_CFG_SYSTEM_TICK_HOOK() { \ | |||
/* System tick event code here.*/ \ | |||
} | |||
/** | |||
* @brief System halt hook. | |||
* @details This hook is invoked in case to a system halting error before | |||
* the system is halted. | |||
*/ | |||
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ | |||
/* System halt code here.*/ \ | |||
} | |||
/** | |||
* @brief Trace hook. | |||
* @details This hook is invoked each time a new record is written in the | |||
* trace buffer. | |||
*/ | |||
#define CH_CFG_TRACE_HOOK(tep) { \ | |||
/* Trace code here.*/ \ | |||
} | |||
/** @} */ | |||
/*===========================================================================*/ | |||
/* Port-specific settings (override port settings defaulted in chcore.h). */ | |||
/*===========================================================================*/ | |||
#endif /* CHCONF_H */ | |||
/** @} */ |
@ -0,0 +1,24 @@ | |||
#pragma once | |||
#include "config_common.h" | |||
/* USB Device descriptor parameter */ | |||
#define VENDOR_ID 0xFEED | |||
#define PRODUCT_ID 0x0C61 | |||
#define DEVICE_VER 0x00C6 | |||
#define MANUFACTURER PeiorisBoards | |||
#define PRODUCT Ixora Rev1 | |||
#define DESCRIPTION 6key Macropad | |||
/* key matrix size */ | |||
#define MATRIX_ROWS 1 | |||
#define MATRIX_COLS 6 | |||
#define MATRIX_ROW_PINS { A0 } | |||
#define MATRIX_COL_PINS { B4, A15, B3, A1, B6, B5 } | |||
/* COL2ROW, ROW2COL, or CUSTOM_MATRIX */ | |||
#define DIODE_DIRECTION COL2ROW | |||
/* Debounce reduces chatter (unintended double-presses) - set 0 if debouncing is not needed */ | |||
#define DEBOUNCE 0 |
@ -0,0 +1,350 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
/** | |||
* @file templates/halconf.h | |||
* @brief HAL configuration header. | |||
* @details HAL configuration file, this file allows to enable or disable the | |||
* various device drivers from your application. You may also use | |||
* this file in order to override the device drivers default settings. | |||
* | |||
* @addtogroup HAL_CONF | |||
* @{ | |||
*/ | |||
#ifndef _HALCONF_H_ | |||
#define _HALCONF_H_ | |||
#include "mcuconf.h" | |||
/** | |||
* @brief Enables the PAL subsystem. | |||
*/ | |||
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) | |||
#define HAL_USE_PAL TRUE | |||
#endif | |||
/** | |||
* @brief Enables the ADC subsystem. | |||
*/ | |||
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) | |||
#define HAL_USE_ADC FALSE | |||
#endif | |||
/** | |||
* @brief Enables the CAN subsystem. | |||
*/ | |||
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) | |||
#define HAL_USE_CAN FALSE | |||
#endif | |||
/** | |||
* @brief Enables the DAC subsystem. | |||
*/ | |||
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) | |||
#define HAL_USE_DAC FALSE | |||
#endif | |||
/** | |||
* @brief Enables the EXT subsystem. | |||
*/ | |||
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) | |||
#define HAL_USE_EXT FALSE | |||
#endif | |||
/** | |||
* @brief Enables the GPT subsystem. | |||
*/ | |||
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) | |||
#define HAL_USE_GPT FALSE | |||
#endif | |||
/** | |||
* @brief Enables the I2C subsystem. | |||
*/ | |||
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) | |||
#define HAL_USE_I2C FALSE | |||
#endif | |||
/** | |||
* @brief Enables the I2S subsystem. | |||
*/ | |||
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) | |||
#define HAL_USE_I2S FALSE | |||
#endif | |||
/** | |||
* @brief Enables the ICU subsystem. | |||
*/ | |||
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) | |||
#define HAL_USE_ICU FALSE | |||
#endif | |||
/** | |||
* @brief Enables the MAC subsystem. | |||
*/ | |||
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) | |||
#define HAL_USE_MAC FALSE | |||
#endif | |||
/** | |||
* @brief Enables the MMC_SPI subsystem. | |||
*/ | |||
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) | |||
#define HAL_USE_MMC_SPI FALSE | |||
#endif | |||
/** | |||
* @brief Enables the PWM subsystem. | |||
*/ | |||
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) | |||
#define HAL_USE_PWM FALSE | |||
#endif | |||
/** | |||
* @brief Enables the RTC subsystem. | |||
*/ | |||
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) | |||
#define HAL_USE_RTC FALSE | |||
#endif | |||
/** | |||
* @brief Enables the SDC subsystem. | |||
*/ | |||
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) | |||
#define HAL_USE_SDC FALSE | |||
#endif | |||
/** | |||
* @brief Enables the SERIAL subsystem. | |||
*/ | |||
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) | |||
#define HAL_USE_SERIAL FALSE | |||
#endif | |||
/** | |||
* @brief Enables the SERIAL over USB subsystem. | |||
*/ | |||
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) | |||
#define HAL_USE_SERIAL_USB TRUE | |||
#endif | |||
/** | |||
* @brief Enables the SPI subsystem. | |||
*/ | |||
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) | |||
#define HAL_USE_SPI FALSE | |||
#endif | |||
/** | |||
* @brief Enables the UART subsystem. | |||
*/ | |||
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) | |||
#define HAL_USE_UART FALSE | |||
#endif | |||
/** | |||
* @brief Enables the USB subsystem. | |||
*/ | |||
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) | |||
#define HAL_USE_USB TRUE | |||
#endif | |||
/** | |||
* @brief Enables the WDG subsystem. | |||
*/ | |||
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) | |||
#define HAL_USE_WDG FALSE | |||
#endif | |||
/*===========================================================================*/ | |||
/* ADC driver related settings. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Enables synchronous APIs. | |||
* @note Disabling this option saves both code and data space. | |||
*/ | |||
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) | |||
#define ADC_USE_WAIT FALSE | |||
#endif | |||
/** | |||
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. | |||
* @note Disabling this option saves both code and data space. | |||
*/ | |||
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) | |||
#define ADC_USE_MUTUAL_EXCLUSION FALSE | |||
#endif | |||
/*===========================================================================*/ | |||
/* CAN driver related settings. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Sleep mode related APIs inclusion switch. | |||
*/ | |||
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) | |||
#define CAN_USE_SLEEP_MODE TRUE | |||
#endif | |||
/*===========================================================================*/ | |||
/* I2C driver related settings. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Enables the mutual exclusion APIs on the I2C bus. | |||
*/ | |||
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) | |||
#define I2C_USE_MUTUAL_EXCLUSION TRUE | |||
#endif | |||
/*===========================================================================*/ | |||
/* MAC driver related settings. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Enables an event sources for incoming packets. | |||
*/ | |||
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) | |||
#define MAC_USE_ZERO_COPY FALSE | |||
#endif | |||
/** | |||
* @brief Enables an event sources for incoming packets. | |||
*/ | |||
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) | |||
#define MAC_USE_EVENTS TRUE | |||
#endif | |||
/*===========================================================================*/ | |||
/* MMC_SPI driver related settings. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Delays insertions. | |||
* @details If enabled this options inserts delays into the MMC waiting | |||
* routines releasing some extra CPU time for the threads with | |||
* lower priority, this may slow down the driver a bit however. | |||
* This option is recommended also if the SPI driver does not | |||
* use a DMA channel and heavily loads the CPU. | |||
*/ | |||
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) | |||
#define MMC_NICE_WAITING TRUE | |||
#endif | |||
/*===========================================================================*/ | |||
/* SDC driver related settings. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Number of initialization attempts before rejecting the card. | |||
* @note Attempts are performed at 10mS intervals. | |||
*/ | |||
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) | |||
#define SDC_INIT_RETRY 100 | |||
#endif | |||
/** | |||
* @brief Include support for MMC cards. | |||
* @note MMC support is not yet implemented so this option must be kept | |||
* at @p FALSE. | |||
*/ | |||
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) | |||
#define SDC_MMC_SUPPORT FALSE | |||
#endif | |||
/** | |||
* @brief Delays insertions. | |||
* @details If enabled this options inserts delays into the MMC waiting | |||
* routines releasing some extra CPU time for the threads with | |||
* lower priority, this may slow down the driver a bit however. | |||
*/ | |||
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) | |||
#define SDC_NICE_WAITING TRUE | |||
#endif | |||
/*===========================================================================*/ | |||
/* SERIAL driver related settings. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Default bit rate. | |||
* @details Configuration parameter, this is the baud rate selected for the | |||
* default configuration. | |||
*/ | |||
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) | |||
#define SERIAL_DEFAULT_BITRATE 38400 | |||
#endif | |||
/** | |||
* @brief Serial buffers size. | |||
* @details Configuration parameter, you can change the depth of the queue | |||
* buffers depending on the requirements of your application. | |||
* @note The default is 64 bytes for both the transmission and receive | |||
* buffers. | |||
*/ | |||
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) | |||
#define SERIAL_BUFFERS_SIZE 16 | |||
#endif | |||
/*===========================================================================*/ | |||
/* SERIAL_USB driver related setting. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Serial over USB buffers size. | |||
* @details Configuration parameter, the buffer size must be a multiple of | |||
* the USB data endpoint maximum packet size. | |||
* @note The default is 64 bytes for both the transmission and receive | |||
* buffers. | |||
*/ | |||
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) | |||
#define SERIAL_USB_BUFFERS_SIZE 256 | |||
#endif | |||
/*===========================================================================*/ | |||
/* SPI driver related settings. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Enables synchronous APIs. | |||
* @note Disabling this option saves both code and data space. | |||
*/ | |||
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) | |||
#define SPI_USE_WAIT FALSE | |||
#endif | |||
/** | |||
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. | |||
* @note Disabling this option saves both code and data space. | |||
*/ | |||
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) | |||
#define SPI_USE_MUTUAL_EXCLUSION FALSE | |||
#endif | |||
/*===========================================================================*/ | |||
/* USB driver related settings. */ | |||
/*===========================================================================*/ | |||
/** | |||
* @brief Enables synchronous APIs. | |||
* @note Disabling this option saves both code and data space. | |||
*/ | |||
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) | |||
#define USB_USE_WAIT TRUE | |||
#endif | |||
#endif /* _HALCONF_H_ */ | |||
/** @} */ |
@ -0,0 +1,21 @@ | |||
{ | |||
"keyboard_name": "Ixora", | |||
"url": "", | |||
"maintainer": "Peioris", | |||
"width": 3, | |||
"height": 2, | |||
"layouts": { | |||
"LAYOUT_full": { | |||
"layout": [{"label":"1", "x":0, "y":0}, {"label":"2", "x":1, "y":0}, {"label":"3", "x":2, "y":0}, {"label":"Caps Lock", "x":0, "y":1}, {"label":"Num Lock", "x":1, "y":1}, {"label":"Scroll Lock", "x":2, "y":1}] | |||
}, | |||
"LAYOUT_blocker_right": { | |||
"layout": [{"label":"1", "x":0, "y":0}, {"label":"2", "x":1, "y":0}, {"label":"Caps Lock", "x":0, "y":1}, {"label":"Num Lock", "x":1, "y":1}, {"label":"Scroll Lock", "x":2, "y":1}] | |||
}, | |||
"LAYOUT_blocker_left": { | |||
"layout": [{"label":"2", "x":1, "y":0}, {"label":"3", "x":2, "y":0}, {"label":"Caps Lock", "x":0, "y":1}, {"label":"Num Lock", "x":1, "y":1}, {"label":"Scroll Lock", "x":2, "y":1}] | |||
}, | |||
"LAYOUT_arrows": { | |||
"layout": [{"label":"\u2191", "x":1, "y":0}, {"label":"\u2190", "x":0, "y":1}, {"label":"\u2193", "x":1, "y":1}, {"label":"\u2192", "x":2, "y":1}] | |||
} | |||
} | |||
} |
@ -0,0 +1,43 @@ | |||
#include "ixora.h" | |||
void matrix_init_kb(void) { | |||
// put your keyboard start-up code here | |||
// runs once when the firmware starts up | |||
setPinOutput(A8); | |||
setPinOutput(A9); | |||
setPinOutput(A10); | |||
writePinLow(A8); | |||
writePinLow(A9); | |||
writePinLow(A10); | |||
matrix_init_user(); | |||
} | |||
void matrix_scan_kb(void) { | |||
matrix_scan_user(); | |||
} | |||
bool process_record_kb(uint16_t keycode, keyrecord_t *record) { | |||
return process_record_user(keycode, record); | |||
} | |||
void led_set_kb(uint8_t usb_led) { | |||
if (IS_LED_ON(usb_led, USB_LED_CAPS_LOCK)) { | |||
writePinHigh(A10); | |||
} else { | |||
writePinLow(A10); | |||
} | |||
if (IS_LED_ON(usb_led, USB_LED_NUM_LOCK)) { | |||
writePinHigh(A9); | |||
} else { | |||
writePinLow(A9); | |||
} | |||
if (IS_LED_ON(usb_led, USB_LED_SCROLL_LOCK)) { | |||
writePinHigh(A8); | |||
} else { | |||
writePinLow(A8); | |||
} | |||
led_set_user(usb_led); | |||
} |
@ -0,0 +1,40 @@ | |||
#pragma once | |||
#define XXX KC_NO | |||
#include "quantum.h" | |||
// This a shortcut to help you visually see your layout. | |||
#define LAYOUT_full( \ | |||
K00, K01, K02, \ | |||
K03, K04, K05 \ | |||
) \ | |||
{ \ | |||
{ K00, K01, K02, K03, K04, K05 } \ | |||
} | |||
#define LAYOUT_blocker_right( \ | |||
K00, K01, \ | |||
K03, K04, K05 \ | |||
) \ | |||
{ \ | |||
{ K00, K01, XXX, K03, K04, K05 } \ | |||
} | |||
#define LAYOUT_blocker_left( \ | |||
K01, K02, \ | |||
K03, K04, K05 \ | |||
) \ | |||
{ \ | |||
{ XXX, K01, K02, K03, K04, K05 } \ | |||
} | |||
#define LAYOUT_arrows( \ | |||
K01, \ | |||
K03, K04, K05 \ | |||
) \ | |||
{ \ | |||
{ XXX, K01, XXX, K03, K04, K05 } \ | |||
} | |||
@ -0,0 +1,42 @@ | |||
/* Copyright 2018 Peioris | |||
* | |||
* This program is free software: you can redistribute it and/or modify | |||
* it under the terms of the GNU General Public License as published by | |||
* the Free Software Foundation, either version 2 of the License, or | |||
* (at your option) any later version. | |||
* | |||
* This program is distributed in the hope that it will be useful, | |||
* but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
* GNU General Public License for more details. | |||
* | |||
* You should have received a copy of the GNU General Public License | |||
* along with this program. If not, see <http://www.gnu.org/licenses/>. | |||
*/ | |||
#include QMK_KEYBOARD_H | |||
const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = { | |||
/* Keymap _BL: (Base Layer) Default Layer | |||
* ,-----------------. | |||
* |RESET| 2 | 3 | | |||
* |-----------------| | |||
* |Caps |NmLk |ScLk | | |||
* `-----------------' | |||
*/ | |||
[0] = LAYOUT_full( | |||
RESET, KC_2, KC_3, | |||
KC_CAPS, KC_NLCK, KC_SLCK) | |||
}; | |||
void matrix_init_user(void) { | |||
//user initialization | |||
} | |||
void matrix_scan_user(void) { | |||
//user matrix | |||
} | |||
bool process_record_user(uint16_t keycode, keyrecord_t *record) { | |||
return true; | |||
} |
@ -0,0 +1,26 @@ | |||
#include QMK_KEYBOARD_H | |||
const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = { | |||
/* Keymap _BL: (Base Layer) Default Layer | |||
* ,-----------------. | |||
* |RESET| 2 | 3 | | |||
* |-----------------| | |||
* |Caps |NmLk |ScLk | | |||
* `-----------------' | |||
*/ | |||
[0] = LAYOUT_full( | |||
KC_PSCR, KC_MUTE, LGUI(KC_1), | |||
KC_MPRV, KC_MPLY, KC_MNXT) | |||
}; | |||
void matrix_init_user(void) { | |||
//user initialization | |||
} | |||
void matrix_scan_user(void) { | |||
//user matrix | |||
} | |||
bool process_record_user(uint16_t keycode, keyrecord_t *record) { | |||
return true; | |||
} |
@ -0,0 +1,168 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
#ifndef _MCUCONF_H_ | |||
#define _MCUCONF_H_ | |||
/* | |||
* STM32F0xx drivers configuration. | |||
* The following settings override the default settings present in | |||
* the various device driver implementation headers. | |||
* Note that the settings for each driver only have effect if the whole | |||
* driver is enabled in halconf.h. | |||
* | |||
* IRQ priorities: | |||
* 3...0 Lowest...Highest. | |||
* | |||
* DMA priorities: | |||
* 0...3 Lowest...Highest. | |||
*/ | |||
#define STM32F0xx_MCUCONF | |||
/* | |||
* HAL driver system settings. | |||
*/ | |||
#define STM32_NO_INIT FALSE | |||
#define STM32_PVD_ENABLE FALSE | |||
#define STM32_PLS STM32_PLS_LEV0 | |||
#define STM32_HSI_ENABLED TRUE | |||
#define STM32_HSI14_ENABLED TRUE | |||
#define STM32_HSI48_ENABLED FALSE | |||
#define STM32_LSI_ENABLED TRUE | |||
#define STM32_HSE_ENABLED FALSE | |||
#define STM32_LSE_ENABLED FALSE | |||
#define STM32_SW STM32_SW_PLL | |||
#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2 | |||
#define STM32_PREDIV_VALUE 1 | |||
#define STM32_PLLMUL_VALUE 12 | |||
#define STM32_HPRE STM32_HPRE_DIV1 | |||
#define STM32_PPRE STM32_PPRE_DIV1 | |||
#define STM32_ADCSW STM32_ADCSW_HSI14 | |||
#define STM32_ADCPRE STM32_ADCPRE_DIV4 | |||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK | |||
#define STM32_ADCPRE STM32_ADCPRE_DIV4 | |||
#define STM32_ADCSW STM32_ADCSW_HSI14 | |||
#define STM32_USBSW STM32_USBSW_HSI48 | |||
#define STM32_CECSW STM32_CECSW_HSI | |||
#define STM32_I2C1SW STM32_I2C1SW_HSI | |||
#define STM32_USART1SW STM32_USART1SW_PCLK | |||
#define STM32_RTCSEL STM32_RTCSEL_LSI | |||
/* | |||
* ADC driver system settings. | |||
*/ | |||
#define STM32_ADC_USE_ADC1 FALSE | |||
#define STM32_ADC_ADC1_DMA_PRIORITY 2 | |||
#define STM32_ADC_IRQ_PRIORITY 2 | |||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 | |||
/* | |||
* EXT driver system settings. | |||
*/ | |||
#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 | |||
#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 | |||
#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 | |||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 | |||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 | |||
/* | |||
* GPT driver system settings. | |||
*/ | |||
#define STM32_GPT_USE_TIM1 FALSE | |||
#define STM32_GPT_USE_TIM2 FALSE | |||
#define STM32_GPT_USE_TIM3 FALSE | |||
#define STM32_GPT_USE_TIM14 FALSE | |||
#define STM32_GPT_TIM1_IRQ_PRIORITY 2 | |||
#define STM32_GPT_TIM2_IRQ_PRIORITY 2 | |||
#define STM32_GPT_TIM3_IRQ_PRIORITY 2 | |||
#define STM32_GPT_TIM14_IRQ_PRIORITY 2 | |||
/* | |||
* I2C driver system settings. | |||
*/ | |||
#define STM32_I2C_USE_I2C1 FALSE | |||
#define STM32_I2C_USE_I2C2 FALSE | |||
#define STM32_I2C_BUSY_TIMEOUT 50 | |||
#define STM32_I2C_I2C1_IRQ_PRIORITY 3 | |||
#define STM32_I2C_I2C2_IRQ_PRIORITY 3 | |||
#define STM32_I2C_USE_DMA TRUE | |||
#define STM32_I2C_I2C1_DMA_PRIORITY 1 | |||
#define STM32_I2C_I2C2_DMA_PRIORITY 1 | |||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") | |||
/* | |||
* ICU driver system settings. | |||
*/ | |||
#define STM32_ICU_USE_TIM1 FALSE | |||
#define STM32_ICU_USE_TIM2 FALSE | |||
#define STM32_ICU_USE_TIM3 FALSE | |||
#define STM32_ICU_TIM1_IRQ_PRIORITY 3 | |||
#define STM32_ICU_TIM2_IRQ_PRIORITY 3 | |||
#define STM32_ICU_TIM3_IRQ_PRIORITY 3 | |||
/* | |||
* PWM driver system settings. | |||
*/ | |||
#define STM32_PWM_USE_ADVANCED FALSE | |||
#define STM32_PWM_USE_TIM1 FALSE | |||
#define STM32_PWM_USE_TIM2 FALSE | |||
#define STM32_PWM_USE_TIM3 FALSE | |||
#define STM32_PWM_TIM1_IRQ_PRIORITY 3 | |||
#define STM32_PWM_TIM2_IRQ_PRIORITY 3 | |||
#define STM32_PWM_TIM3_IRQ_PRIORITY 3 | |||
/* | |||
* SERIAL driver system settings. | |||
*/ | |||
#define STM32_SERIAL_USE_USART1 FALSE | |||
#define STM32_SERIAL_USE_USART2 FALSE | |||
#define STM32_SERIAL_USART1_PRIORITY 3 | |||
#define STM32_SERIAL_USART2_PRIORITY 3 | |||
/* | |||
* SPI driver system settings. | |||
*/ | |||
#define STM32_SPI_USE_SPI1 FALSE | |||
#define STM32_SPI_USE_SPI2 FALSE | |||
#define STM32_SPI_SPI1_DMA_PRIORITY 1 | |||
#define STM32_SPI_SPI2_DMA_PRIORITY 1 | |||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2 | |||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2 | |||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") | |||
/* | |||
* ST driver system settings. | |||
*/ | |||
#define STM32_ST_IRQ_PRIORITY 2 | |||
#define STM32_ST_USE_TIMER 2 | |||
/* | |||
* UART driver system settings. | |||
*/ | |||
#define STM32_UART_USE_USART1 FALSE | |||
#define STM32_UART_USE_USART2 FALSE | |||
#define STM32_UART_USART1_IRQ_PRIORITY 3 | |||
#define STM32_UART_USART2_IRQ_PRIORITY 3 | |||
#define STM32_UART_USART1_DMA_PRIORITY 0 | |||
#define STM32_UART_USART2_DMA_PRIORITY 0 | |||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") | |||
/* | |||
* USB driver system settings. | |||
*/ | |||
#define STM32_USB_USE_USB1 TRUE | |||
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE | |||
#define STM32_USB_USB1_LP_IRQ_PRIORITY 3 | |||
#endif /* _MCUCONF_H_ */ |
@ -0,0 +1,22 @@ | |||
Ixora | |||
========= | |||
[Ixora](https://i.imgur.com/GqDk3XY.png) | |||
Ixora is an ARM-powered 6-key macropad with a USB connector, hotswap sockets, and indicator LEDs. | |||
Keyboard Maintainer: [Peioris](https://github.com/coarse) | |||
Hardware Supported: Ixora PCB | |||
Hardware Availability: [Peioris](https://github.com/coarse) | |||
Make example for this keyboard (after setting up your build environment): | |||
make peiorisboards/ixora:default:dfu-util | |||
See [build environment setup](https://docs.qmk.fm/build_environment_setup.html) then the [make instructions](https://docs.qmk.fm/make_instructions.html) for more information. | |||
#### Developer's Note | |||
STM32F042xx chips does not allow jumping to bootloader without BOOT0 being set to high, therefore it is impossible to enter the bootloader from sending a `RESET` keycode nor using bootmagic or bootmagic lite. | |||
The only way to enter bootloader is to hold the BOOT0 button while the keyboard is powering up or after a power reset (done by pressing the reset switch or sending a `RESET` keycode). |
@ -0,0 +1,47 @@ | |||
# project specific files | |||
## chip/board settings | |||
# - the next two should match the directories in | |||
# <chibios>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES) | |||
MCU_FAMILY = STM32 | |||
MCU_SERIES = STM32F0xx | |||
# Linker script to use | |||
# - it should exist either in <chibios>/os/common/ports/ARMCMx/compilers/GCC/ld/ | |||
# or <this_dir>/ld/ | |||
MCU_LDSCRIPT = STM32F042x6 | |||
# Startup code to use | |||
# - it should exist in <chibios>/os/common/ports/ARMCMx/compilers/GCC/mk/ | |||
MCU_STARTUP = stm32f0xx | |||
# Board: it should exist either in <chibios>/os/hal/boards/ | |||
# or <this_dir>/boards | |||
BOARD = GENERIC_STM32_F042X6 | |||
# Cortex version | |||
MCU = cortex-m0 | |||
# ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7 | |||
ARMV = 6 | |||
# Vector table for application | |||
# 0x00000000-0x00001000 area is occupied by bootlaoder.*/ | |||
# The CORTEX_VTOR... is needed only for MCHCK/Infinity KB | |||
#OPT_DEFS = -DCORTEX_VTOR_INIT=0x00001000 | |||
OPT_DEFS = | |||
# Options to pass to dfu-util when flashing | |||
DFU_ARGS = -d 0483:df11 -a 0 -s 0x08000000:leave | |||
# Build Options | |||
# comment out to disable the options. | |||
# | |||
BACKLIGHT_ENABLE = no | |||
BOOTMAGIC_ENABLE = yes # Virtual DIP switch configuration | |||
MOUSEKEY_ENABLE = yes # Mouse keys | |||
EXTRAKEY_ENABLE = yes # Audio control and System control | |||
CONSOLE_ENABLE = no # Console for debug | |||
COMMAND_ENABLE = no # Commands for debug and configuration | |||
NKRO_ENABLE = yes # USB Nkey Rollover | |||
NO_USB_STARTUP_CHECK = no # Disable initialization only when usb is plugged in |