|
@ -9,23 +9,26 @@ |
|
|
|
|
|
|
|
|
#include "i2c_slave.h" |
|
|
#include "i2c_slave.h" |
|
|
|
|
|
|
|
|
void i2c_init(uint8_t address){ |
|
|
|
|
|
|
|
|
volatile uint8_t i2c_slave_reg[I2C_SLAVE_REG_COUNT]; |
|
|
|
|
|
|
|
|
|
|
|
static volatile uint8_t buffer_address; |
|
|
|
|
|
static volatile bool slave_has_register_set = false; |
|
|
|
|
|
|
|
|
|
|
|
void i2c_slave_init(uint8_t address){ |
|
|
// load address into TWI address register |
|
|
// load address into TWI address register |
|
|
TWAR = (address << 1); |
|
|
TWAR = (address << 1); |
|
|
// set the TWCR to enable address matching and enable TWI, clear TWINT, enable TWI interrupt |
|
|
// set the TWCR to enable address matching and enable TWI, clear TWINT, enable TWI interrupt |
|
|
TWCR = (1 << TWIE) | (1 << TWEA) | (1 << TWINT) | (1 << TWEN); |
|
|
TWCR = (1 << TWIE) | (1 << TWEA) | (1 << TWINT) | (1 << TWEN); |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
void i2c_stop(void){ |
|
|
|
|
|
|
|
|
void i2c_slave_stop(void){ |
|
|
// clear acknowledge and enable bits |
|
|
// clear acknowledge and enable bits |
|
|
TWCR &= ~((1 << TWEA) | (1 << TWEN)); |
|
|
TWCR &= ~((1 << TWEA) | (1 << TWEN)); |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
ISR(TWI_vect){ |
|
|
ISR(TWI_vect){ |
|
|
uint8_t ack = 1; |
|
|
uint8_t ack = 1; |
|
|
// temporary stores the received data |
|
|
|
|
|
//uint8_t data; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
switch(TW_STATUS){ |
|
|
switch(TW_STATUS){ |
|
|
case TW_SR_SLA_ACK: |
|
|
case TW_SR_SLA_ACK: |
|
|
// The device is now a slave receiver |
|
|
// The device is now a slave receiver |
|
@ -38,13 +41,13 @@ ISR(TWI_vect){ |
|
|
if(!slave_has_register_set){ |
|
|
if(!slave_has_register_set){ |
|
|
buffer_address = TWDR; |
|
|
buffer_address = TWDR; |
|
|
|
|
|
|
|
|
if (buffer_address >= RX_BUFFER_SIZE){ // address out of bounds dont ack |
|
|
|
|
|
ack = 0; |
|
|
|
|
|
buffer_address = 0; |
|
|
|
|
|
|
|
|
if (buffer_address >= I2C_SLAVE_REG_COUNT) { // address out of bounds dont ack |
|
|
|
|
|
ack = 0; |
|
|
|
|
|
buffer_address = 0; |
|
|
} |
|
|
} |
|
|
slave_has_register_set = true; // address has been receaved now fill in buffer |
|
|
slave_has_register_set = true; // address has been receaved now fill in buffer |
|
|
} else { |
|
|
} else { |
|
|
rxbuffer[buffer_address] = TWDR; |
|
|
|
|
|
|
|
|
i2c_slave_reg[buffer_address] = TWDR; |
|
|
buffer_address++; |
|
|
buffer_address++; |
|
|
} |
|
|
} |
|
|
break; |
|
|
break; |
|
@ -52,7 +55,7 @@ ISR(TWI_vect){ |
|
|
case TW_ST_SLA_ACK: |
|
|
case TW_ST_SLA_ACK: |
|
|
case TW_ST_DATA_ACK: |
|
|
case TW_ST_DATA_ACK: |
|
|
// This device is a slave transmitter and master has requested data |
|
|
// This device is a slave transmitter and master has requested data |
|
|
TWDR = txbuffer[buffer_address]; |
|
|
|
|
|
|
|
|
TWDR = i2c_slave_reg[buffer_address]; |
|
|
buffer_address++; |
|
|
buffer_address++; |
|
|
break; |
|
|
break; |
|
|
|
|
|
|
|
@ -63,6 +66,6 @@ ISR(TWI_vect){ |
|
|
break; |
|
|
break; |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
// Reset i2c state mahcine to be ready for next interrupt |
|
|
|
|
|
|
|
|
// Reset i2c state machine to be ready for next interrupt |
|
|
TWCR |= (1 << TWIE) | (1 << TWINT) | (ack << TWEA) | (1 << TWEN); |
|
|
TWCR |= (1 << TWIE) | (1 << TWINT) | (ack << TWEA) | (1 << TWEN); |
|
|
} |
|
|
} |