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// Copyright 2023-2024 HorrorTroll <https://github.com/HorrorTroll> | |||
// Copyright 2023-2024 Zhaqian <https://github.com/zhaqian12> | |||
// SPDX-License-Identifier: GPL-2.0-or-later | |||
#pragma once | |||
#include_next <board.h> | |||
#undef AT32F415KB | |||
#define AT32F415RC |
@ -0,0 +1,7 @@ | |||
// Copyright 2023-2024 HorrorTroll <https://github.com/HorrorTroll> | |||
// Copyright 2023-2024 Zhaqian <https://github.com/zhaqian12> | |||
// SPDX-License-Identifier: GPL-2.0-or-later | |||
#pragma once | |||
#define ADC_PIN A0 |
@ -0,0 +1,11 @@ | |||
// Copyright 2023-2024 HorrorTroll <https://github.com/HorrorTroll> | |||
// Copyright 2023-2024 Zhaqian <https://github.com/zhaqian12> | |||
// SPDX-License-Identifier: GPL-2.0-or-later | |||
#pragma once | |||
#define HAL_USE_ADC TRUE | |||
#define HAL_USE_I2C TRUE | |||
#include_next <halconf.h> |
@ -0,0 +1,12 @@ | |||
{ | |||
"keyboard_name": "Onekey AT-START-F415", | |||
"processor": "AT32F415", | |||
"bootloader": "at32-dfu", | |||
"matrix_pins": { | |||
"cols": ["B3"], | |||
"rows": ["B4"] | |||
}, | |||
"ws2812": { | |||
"pin": "B0" | |||
} | |||
} |
@ -0,0 +1,13 @@ | |||
// Copyright 2023-2024 HorrorTroll <https://github.com/HorrorTroll> | |||
// Copyright 2023-2024 Zhaqian <https://github.com/zhaqian12> | |||
// SPDX-License-Identifier: GPL-2.0-or-later | |||
#pragma once | |||
#include_next <mcuconf.h> | |||
#undef AT32_ADC_USE_ADC1 | |||
#define AT32_ADC_USE_ADC1 TRUE | |||
#undef AT32_I2C_USE_I2C1 | |||
#define AT32_I2C_USE_I2C1 TRUE |
@ -0,0 +1,3 @@ | |||
# Artery AT-START-F415 Board Onekey | |||
To trigger keypress, short together pins *B3* and *B4*. |
@ -0,0 +1 @@ | |||
KEYBOARD_SHARED_EP = yes |
@ -0,0 +1,55 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | |||
ChibiOS - Copyright (C) 2023..2024 HorrorTroll | |||
ChibiOS - Copyright (C) 2023..2024 Zhaqian | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
#include "hal.h" | |||
/** | |||
* @brief PAL setup. | |||
* @details Digital I/O ports static configuration as defined in @p board.h. | |||
* This variable is used by the HAL when initializing the PAL driver. | |||
*/ | |||
#if HAL_USE_PAL || defined(__DOXYGEN__) | |||
const PALConfig pal_default_config = | |||
{ | |||
{VAL_GPIOAODT, VAL_GPIOACFGLR, VAL_GPIOACFGHR}, | |||
{VAL_GPIOBODT, VAL_GPIOBCFGLR, VAL_GPIOBCFGHR}, | |||
#if AT32_HAS_GPIOC | |||
{VAL_GPIOCODT, VAL_GPIOCCFGLR, VAL_GPIOCCFGHR}, | |||
#endif | |||
{VAL_GPIODODT, VAL_GPIODCFGLR, VAL_GPIODCFGHR}, | |||
#if AT32_HAS_GPIOF | |||
{VAL_GPIOFODT, VAL_GPIOFCFGLR, VAL_GPIOFCFGHR}, | |||
#endif | |||
}; | |||
#endif | |||
/* | |||
* Early initialization code. | |||
* This initialization must be performed just after stack setup and before | |||
* any other initialization. | |||
*/ | |||
void __early_init(void) { | |||
at32_clock_init(); | |||
} | |||
/* | |||
* Board-specific initialization code. | |||
*/ | |||
void boardInit(void) { | |||
IOMUX->REMAP |= IOMUX_REMAP_SWJTAG_MUX_JTAGDIS; | |||
} |
@ -0,0 +1,203 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | |||
ChibiOS - Copyright (C) 2023..2024 HorrorTroll | |||
ChibiOS - Copyright (C) 2023..2024 Zhaqian | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
#ifndef _BOARD_H_ | |||
#define _BOARD_H_ | |||
/* | |||
* Setup for a Generic AT32F415 board. | |||
*/ | |||
/* | |||
* Board identifier. | |||
*/ | |||
#define BOARD_GENERIC_AT32_F415XX | |||
#define BOARD_NAME "GENERIC AT32F415 board" | |||
/* | |||
* Board frequencies. | |||
*/ | |||
#define AT32_LEXTCLK 32768 | |||
#define AT32_HEXTCLK 8000000 | |||
/* | |||
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. | |||
*/ | |||
#define AT32F415KB | |||
/* | |||
* IO pins assignments. | |||
*/ | |||
#define GPIOA_PIN0 0U | |||
#define GPIOA_PIN1 1U | |||
#define GPIOA_PIN2 2U | |||
#define GPIOA_PIN3 3U | |||
#define GPIOA_PIN4 4U | |||
#define GPIOA_PIN5 5U | |||
#define GPIOA_PIN6 6U | |||
#define GPIOA_PIN7 7U | |||
#define GPIOA_PIN8 8U | |||
#define GPIOA_PIN9 9U | |||
#define GPIOA_PIN10 10U | |||
#define GPIOA_PIN11 11U | |||
#define GPIOA_PIN12 12U | |||
#define GPIOA_PIN13 13U | |||
#define GPIOA_PIN14 14U | |||
#define GPIOA_PIN15 15U | |||
#define GPIOB_PIN0 0U | |||
#define GPIOB_PIN1 1U | |||
#define GPIOB_PIN2 2U | |||
#define GPIOB_PIN3 3U | |||
#define GPIOB_PIN4 4U | |||
#define GPIOB_PIN5 5U | |||
#define GPIOB_PIN6 6U | |||
#define GPIOB_PIN7 7U | |||
#define GPIOB_PIN8 8U | |||
#define GPIOB_PIN9 9U | |||
#define GPIOB_PIN10 10U | |||
#define GPIOB_PIN11 11U | |||
#define GPIOB_PIN12 12U | |||
#define GPIOB_PIN13 13U | |||
#define GPIOB_PIN14 14U | |||
#define GPIOB_PIN15 15U | |||
#define GPIOC_PIN0 0U | |||
#define GPIOC_PIN1 1U | |||
#define GPIOC_PIN2 2U | |||
#define GPIOC_PIN3 3U | |||
#define GPIOC_PIN4 4U | |||
#define GPIOC_PIN5 5U | |||
#define GPIOC_PIN6 6U | |||
#define GPIOC_PIN7 7U | |||
#define GPIOC_PIN8 8U | |||
#define GPIOC_PIN9 9U | |||
#define GPIOC_PIN10 10U | |||
#define GPIOC_PIN11 11U | |||
#define GPIOC_PIN12 12U | |||
#define GPIOC_PIN13 13U | |||
#define GPIOC_PIN14 14U | |||
#define GPIOC_PIN15 15U | |||
#define GPIOD_PIN0 0U | |||
#define GPIOD_PIN1 1U | |||
#define GPIOD_PIN2 2U | |||
#define GPIOD_PIN3 3U | |||
#define GPIOD_PIN4 4U | |||
#define GPIOD_PIN5 5U | |||
#define GPIOD_PIN6 6U | |||
#define GPIOD_PIN7 7U | |||
#define GPIOD_PIN8 8U | |||
#define GPIOD_PIN9 9U | |||
#define GPIOD_PIN10 10U | |||
#define GPIOD_PIN11 11U | |||
#define GPIOD_PIN12 12U | |||
#define GPIOD_PIN13 13U | |||
#define GPIOD_PIN14 14U | |||
#define GPIOD_PIN15 15U | |||
#define GPIOF_PIN0 0U | |||
#define GPIOF_PIN1 1U | |||
#define GPIOF_PIN2 2U | |||
#define GPIOF_PIN3 3U | |||
#define GPIOF_PIN4 4U | |||
#define GPIOF_PIN5 5U | |||
#define GPIOF_PIN6 6U | |||
#define GPIOF_PIN7 7U | |||
#define GPIOF_PIN8 8U | |||
#define GPIOF_PIN9 9U | |||
#define GPIOF_PIN10 10U | |||
#define GPIOF_PIN11 11U | |||
#define GPIOF_PIN12 12U | |||
#define GPIOF_PIN13 13U | |||
#define GPIOF_PIN14 14U | |||
#define GPIOF_PIN15 15U | |||
/* | |||
* I/O ports initial setup, this configuration is established soon after reset | |||
* in the initialization code. | |||
* | |||
* The digits have the following meaning: | |||
* 0 - Analog input. | |||
* 1 - Push Pull output 10MHz. | |||
* 2 - Push Pull output 2MHz. | |||
* 3 - Push Pull output 50MHz. | |||
* 4 - Digital input. | |||
* 5 - Open Drain output 10MHz. | |||
* 6 - Open Drain output 2MHz. | |||
* 7 - Open Drain output 50MHz. | |||
* 8 - Digital input with Pull-Up or Pull-Down resistor depending on ODT. | |||
* 9 - Alternate Push Pull output 10MHz. | |||
* A - Alternate Push Pull output 2MHz. | |||
* B - Alternate Push Pull output 50MHz. | |||
* C - Reserved. | |||
* D - Alternate Open Drain output 10MHz. | |||
* E - Alternate Open Drain output 2MHz. | |||
* F - Alternate Open Drain output 50MHz. | |||
* Please refer to the AT32 Reference Manual for details. | |||
*/ | |||
/* | |||
* Port A setup. | |||
*/ | |||
#define VAL_GPIOACFGLR 0x88888B88 /* PA7...PA0 */ | |||
#define VAL_GPIOACFGHR 0x888888B8 /* PA15...PA8 */ | |||
#define VAL_GPIOAODT 0xFFFFFFFF | |||
/* | |||
* Port B setup. | |||
*/ | |||
#define VAL_GPIOBCFGLR 0x88888888 /* PB7...PB0 */ | |||
#define VAL_GPIOBCFGHR 0x88888888 /* PB15...PB8 */ | |||
#define VAL_GPIOBODT 0xFFFFFFFF | |||
/* | |||
* Port C setup. | |||
*/ | |||
#define VAL_GPIOCCFGLR 0x88888888 /* PC7...PC0 */ | |||
#define VAL_GPIOCCFGHR 0x88888888 /* PC15...PC8 */ | |||
#define VAL_GPIOCODT 0xFFFFFFFF | |||
/* | |||
* Port D setup. | |||
* Everything input with pull-up except: | |||
* PD0 - Normal input (XTAL). | |||
* PD1 - Normal input (XTAL). | |||
*/ | |||
#define VAL_GPIODCFGLR 0x88888844 /* PD7...PD0 */ | |||
#define VAL_GPIODCFGHR 0x88888888 /* PD15...PD8 */ | |||
#define VAL_GPIODODT 0xFFFFFFFF | |||
/* | |||
* Port F setup. | |||
*/ | |||
#define VAL_GPIOFCFGLR 0x88888888 /* PF7...PF0 */ | |||
#define VAL_GPIOFCFGHR 0x88888888 /* PF15...PF8 */ | |||
#define VAL_GPIOFODT 0xFFFFFFFF | |||
#if !defined(_FROM_ASM_) | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
void boardInit(void); | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* _FROM_ASM_ */ | |||
#endif /* _BOARD_H_ */ |
@ -0,0 +1,9 @@ | |||
# List of all the board related files. | |||
BOARDSRC = $(BOARD_PATH)/board/board.c | |||
# Required include directories | |||
BOARDINC = $(BOARD_PATH)/board | |||
# Shared variables | |||
ALLCSRC += $(BOARDSRC) | |||
ALLINC += $(BOARDINC) |
@ -0,0 +1,13 @@ | |||
// Copyright 2023-2024 HorrorTroll <https://github.com/HorrorTroll> | |||
// Copyright 2023-2024 Zhaqian <https://github.com/zhaqian12> | |||
// SPDX-License-Identifier: GPL-2.0-or-later | |||
#pragma once | |||
#define BOARD_OTG_VBUSIG | |||
#define USB_ENDPOINTS_ARE_REORDERABLE | |||
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP | |||
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE | |||
#endif |
@ -0,0 +1,222 @@ | |||
/* | |||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | |||
ChibiOS - Copyright (C) 2023..2024 HorrorTroll | |||
ChibiOS - Copyright (C) 2023..2024 Zhaqian | |||
Licensed under the Apache License, Version 2.0 (the "License"); | |||
you may not use this file except in compliance with the License. | |||
You may obtain a copy of the License at | |||
http://www.apache.org/licenses/LICENSE-2.0 | |||
Unless required by applicable law or agreed to in writing, software | |||
distributed under the License is distributed on an "AS IS" BASIS, | |||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||
See the License for the specific language governing permissions and | |||
limitations under the License. | |||
*/ | |||
#ifndef MCUCONF_H | |||
#define MCUCONF_H | |||
#define AT32F415_MCUCONF | |||
/* | |||
* AT32F415 drivers configuration. | |||
* The following settings override the default settings present in | |||
* the various device driver implementation headers. | |||
* Note that the settings for each driver only have effect if the whole | |||
* driver is enabled in halconf.h. | |||
* | |||
* IRQ priorities: | |||
* 15...0 Lowest...Highest. | |||
* | |||
* DMA priorities: | |||
* 0...3 Lowest...Highest. | |||
*/ | |||
/* | |||
* HAL driver system settings. | |||
*/ | |||
#define AT32_NO_INIT FALSE | |||
#define AT32_HICK_ENABLED TRUE | |||
#define AT32_LICK_ENABLED FALSE | |||
#define AT32_HEXT_ENABLED TRUE | |||
#define AT32_LEXT_ENABLED FALSE | |||
#define AT32_SCLKSEL AT32_SCLKSEL_PLL | |||
#define AT32_PLLRCS AT32_PLLRCS_HEXT | |||
#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 | |||
#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID | |||
#define AT32_PLLMULT_VALUE 18 | |||
#define AT32_PLL_FR_VALUE 4 | |||
#define AT32_PLL_MS_VALUE 1 | |||
#define AT32_PLL_NS_VALUE 72 | |||
#define AT32_AHBDIV AT32_AHBDIV_DIV1 | |||
#define AT32_APB1DIV AT32_APB1DIV_DIV2 | |||
#define AT32_APB2DIV AT32_APB2DIV_DIV2 | |||
#define AT32_ADCDIV AT32_ADCDIV_DIV4 | |||
#define AT32_USB_CLOCK_REQUIRED TRUE | |||
#define AT32_USBDIV AT32_USBDIV_DIV3 | |||
#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK | |||
#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV | |||
#define AT32_PVM_ENABLE FALSE | |||
#define AT32_PVMSEL AT32_PVMSEL_LEV1 | |||
/* | |||
* IRQ system settings. | |||
*/ | |||
#define AT32_IRQ_EXINT0_PRIORITY 6 | |||
#define AT32_IRQ_EXINT1_PRIORITY 6 | |||
#define AT32_IRQ_EXINT2_PRIORITY 6 | |||
#define AT32_IRQ_EXINT3_PRIORITY 6 | |||
#define AT32_IRQ_EXINT4_PRIORITY 6 | |||
#define AT32_IRQ_EXINT5_9_PRIORITY 6 | |||
#define AT32_IRQ_EXINT10_15_PRIORITY 6 | |||
#define AT32_IRQ_EXINT16_PRIORITY 6 | |||
#define AT32_IRQ_EXINT17_PRIORITY 15 | |||
#define AT32_IRQ_EXINT18_PRIORITY 6 | |||
#define AT32_IRQ_EXINT19_PRIORITY 6 | |||
#define AT32_IRQ_EXINT20_PRIORITY 6 | |||
#define AT32_IRQ_EXINT21_PRIORITY 15 | |||
#define AT32_IRQ_EXINT22_PRIORITY 15 | |||
#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 | |||
#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 | |||
#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 | |||
#define AT32_IRQ_TMR1_CH_PRIORITY 7 | |||
#define AT32_IRQ_TMR2_PRIORITY 7 | |||
#define AT32_IRQ_TMR3_PRIORITY 7 | |||
#define AT32_IRQ_TMR4_PRIORITY 7 | |||
#define AT32_IRQ_TMR5_PRIORITY 7 | |||
#define AT32_IRQ_USART1_PRIORITY 12 | |||
#define AT32_IRQ_USART2_PRIORITY 12 | |||
#define AT32_IRQ_USART3_PRIORITY 12 | |||
#define AT32_IRQ_UART4_PRIORITY 12 | |||
#define AT32_IRQ_UART5_PRIORITY 12 | |||
/* | |||
* ADC driver system settings. | |||
*/ | |||
#define AT32_ADC_USE_ADC1 FALSE | |||
#define AT32_ADC_ADC1_DMA_PRIORITY 2 | |||
#define AT32_ADC_ADC1_IRQ_PRIORITY 6 | |||
/* | |||
* CAN driver system settings. | |||
*/ | |||
#define AT32_CAN_USE_CAN1 FALSE | |||
#define AT32_CAN_CAN1_IRQ_PRIORITY 11 | |||
/* | |||
* DMA driver system settings. | |||
*/ | |||
#define AT32_DMA_USE_DMAMUX TRUE | |||
/* | |||
* GPT driver system settings. | |||
*/ | |||
#define AT32_GPT_USE_TMR1 FALSE | |||
#define AT32_GPT_USE_TMR2 FALSE | |||
#define AT32_GPT_USE_TMR3 FALSE | |||
#define AT32_GPT_USE_TMR4 FALSE | |||
#define AT32_GPT_USE_TMR5 FALSE | |||
#define AT32_GPT_USE_TMR9 FALSE | |||
#define AT32_GPT_USE_TMR10 FALSE | |||
#define AT32_GPT_USE_TMR11 FALSE | |||
/* | |||
* I2C driver system settings. | |||
*/ | |||
#define AT32_I2C_USE_I2C1 FALSE | |||
#define AT32_I2C_USE_I2C2 FALSE | |||
#define AT32_I2C_BUSY_TIMEOUT 50 | |||
#define AT32_I2C_I2C1_IRQ_PRIORITY 5 | |||
#define AT32_I2C_I2C2_IRQ_PRIORITY 5 | |||
#define AT32_I2C_I2C1_DMA_PRIORITY 3 | |||
#define AT32_I2C_I2C2_DMA_PRIORITY 3 | |||
#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") | |||
/* | |||
* ICU driver system settings. | |||
*/ | |||
#define AT32_ICU_USE_TMR1 FALSE | |||
#define AT32_ICU_USE_TMR2 FALSE | |||
#define AT32_ICU_USE_TMR3 FALSE | |||
#define AT32_ICU_USE_TMR4 FALSE | |||
#define AT32_ICU_USE_TMR5 FALSE | |||
#define AT32_ICU_USE_TMR9 FALSE | |||
#define AT32_ICU_USE_TMR10 FALSE | |||
#define AT32_ICU_USE_TMR11 FALSE | |||
/* | |||
* PWM driver system settings. | |||
*/ | |||
#define AT32_PWM_USE_TMR1 FALSE | |||
#define AT32_PWM_USE_TMR2 FALSE | |||
#define AT32_PWM_USE_TMR3 FALSE | |||
#define AT32_PWM_USE_TMR4 FALSE | |||
#define AT32_PWM_USE_TMR5 FALSE | |||
#define AT32_PWM_USE_TMR9 FALSE | |||
#define AT32_PWM_USE_TMR10 FALSE | |||
#define AT32_PWM_USE_TMR11 FALSE | |||
/* | |||
* RTC driver system settings. | |||
*/ | |||
#define AT32_ERTC_DIVA_VALUE 32 | |||
#define AT32_ERTC_DIVB_VALUE 1024 | |||
#define AT32_ERTC_CTRL_INIT 0 | |||
#define AT32_ERTC_TAMP_INIT 0 | |||
/* | |||
* SERIAL driver system settings. | |||
*/ | |||
#define AT32_SERIAL_USE_USART1 FALSE | |||
#define AT32_SERIAL_USE_USART2 FALSE | |||
#define AT32_SERIAL_USE_USART3 FALSE | |||
#define AT32_SERIAL_USE_UART4 FALSE | |||
#define AT32_SERIAL_USE_UART5 FALSE | |||
/* | |||
* SPI driver system settings. | |||
*/ | |||
#define AT32_SPI_USE_SPI1 FALSE | |||
#define AT32_SPI_USE_SPI2 FALSE | |||
#define AT32_SPI_SPI1_DMA_PRIORITY 1 | |||
#define AT32_SPI_SPI2_DMA_PRIORITY 1 | |||
#define AT32_SPI_SPI1_IRQ_PRIORITY 10 | |||
#define AT32_SPI_SPI2_IRQ_PRIORITY 10 | |||
#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") | |||
/* | |||
* ST driver system settings. | |||
*/ | |||
#define AT32_ST_IRQ_PRIORITY 8 | |||
#define AT32_ST_USE_TIMER 2 | |||
/* | |||
* UART driver system settings. | |||
*/ | |||
#define AT32_UART_USE_USART1 FALSE | |||
#define AT32_UART_USE_USART2 FALSE | |||
#define AT32_UART_USE_USART3 FALSE | |||
#define AT32_UART_USART1_DMA_PRIORITY 0 | |||
#define AT32_UART_USART2_DMA_PRIORITY 0 | |||
#define AT32_UART_USART3_DMA_PRIORITY 0 | |||
#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") | |||
/* | |||
* USB driver system settings. | |||
*/ | |||
#define AT32_USB_USE_OTG1 TRUE | |||
#define AT32_USB_OTG1_IRQ_PRIORITY 14 | |||
#define AT32_USB_OTG1_RX_FIFO_SIZE 512 | |||
#define AT32_USB_HOST_WAKEUP_DURATION 2 | |||
/* | |||
* WDG driver system settings. | |||
*/ | |||
#define AT32_WDG_USE_WDT FALSE | |||
#endif /* MCUCONF_H */ |
@ -0,0 +1,83 @@ | |||
// Copyright 2021-2023 QMK | |||
// Copyright 2023-2024 HorrorTroll <https://github.com/HorrorTroll> | |||
// Copyright 2023-2024 Zhaqian <https://github.com/zhaqian12> | |||
// SPDX-License-Identifier: GPL-2.0-or-later | |||
#include "bootloader.h" | |||
#include "util.h" | |||
#include <ch.h> | |||
#include <hal.h> | |||
#include "wait.h" | |||
#ifndef AT32_BOOTLOADER_RAM_SYMBOL | |||
# define AT32_BOOTLOADER_RAM_SYMBOL __ram0_end__ | |||
#endif | |||
extern uint32_t AT32_BOOTLOADER_RAM_SYMBOL; | |||
/* This code should be checked whether it runs correctly on platforms */ | |||
#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0)) | |||
#define BOOTLOADER_MAGIC 0xDEADBEEF | |||
#define MAGIC_ADDR (unsigned long *)(SYMVAL(AT32_BOOTLOADER_RAM_SYMBOL) - 4) | |||
__attribute__((weak)) void bootloader_marker_enable(void) { | |||
uint32_t *marker = (uint32_t *)MAGIC_ADDR; | |||
*marker = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader | |||
} | |||
__attribute__((weak)) bool bootloader_marker_active(void) { | |||
const uint32_t *marker = (const uint32_t *)MAGIC_ADDR; | |||
return (*marker == BOOTLOADER_MAGIC) ? true : false; | |||
} | |||
__attribute__((weak)) void bootloader_marker_disable(void) { | |||
uint32_t *marker = (uint32_t *)MAGIC_ADDR; | |||
*marker = 0; | |||
} | |||
__attribute__((weak)) void bootloader_jump(void) { | |||
bootloader_marker_enable(); | |||
NVIC_SystemReset(); | |||
} | |||
__attribute__((weak)) void mcu_reset(void) { | |||
NVIC_SystemReset(); | |||
} | |||
void enter_bootloader_mode_if_requested(void) { | |||
if (bootloader_marker_active()) { | |||
bootloader_marker_disable(); | |||
struct system_memory_vector_t { | |||
uint32_t stack_top; | |||
void (*entrypoint)(void); | |||
}; | |||
const struct system_memory_vector_t *bootloader = (const struct system_memory_vector_t *)(AT32_BOOTLOADER_ADDRESS); | |||
__disable_irq(); | |||
#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) | |||
ARM_MPU_Disable(); | |||
#endif | |||
SysTick->CTRL = 0; | |||
SysTick->VAL = 0; | |||
SysTick->LOAD = 0; | |||
// Clear interrupt enable and interrupt pending registers | |||
for (int i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) { | |||
NVIC->ICER[i] = 0xFFFFFFFF; | |||
NVIC->ICPR[i] = 0xFFFFFFFF; | |||
} | |||
__set_CONTROL(0); | |||
__set_MSP(bootloader->stack_top); | |||
__enable_irq(); | |||
// Jump to bootloader | |||
bootloader->entrypoint(); | |||
while (true) { | |||
} | |||
} | |||
} |