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294 lines
8.8 KiB
294 lines
8.8 KiB
/* Copyright 2020 Christopher Courtney, aka Drashna Jael're (@drashna) <drashna@live.com>
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* Copyright 2019 Sunjun Kim
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* Copyright 2020 Ploopy Corporation
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "spi_master.h"
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#include "pmw3389.h"
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#include "wait.h"
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#include "debug.h"
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#include "print.h"
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#include "pmw3389_firmware.h"
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// Registers
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// clang-format off
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#define REG_Product_ID 0x00
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#define REG_Revision_ID 0x01
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#define REG_Motion 0x02
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#define REG_Delta_X_L 0x03
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#define REG_Delta_X_H 0x04
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#define REG_Delta_Y_L 0x05
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#define REG_Delta_Y_H 0x06
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#define REG_SQUAL 0x07
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#define REG_RawData_Sum 0x08
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#define REG_Maximum_RawData 0x09
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#define REG_Minimum_RawData 0x0a
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#define REG_Shutter_Lower 0x0b
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#define REG_Shutter_Upper 0x0c
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#define REG_Ripple_Control 0x0d
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#define REG_Resolution_L 0x0e
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#define REG_Resolution_H 0x0f
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#define REG_Config2 0x10
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#define REG_Angle_Tune 0x11
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#define REG_Frame_Capture 0x12
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#define REG_SROM_Enable 0x13
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#define REG_Run_Downshift 0x14
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#define REG_Rest1_Rate_Lower 0x15
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#define REG_Rest1_Rate_Upper 0x16
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#define REG_Rest1_Downshift 0x17
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#define REG_Rest2_Rate_Lower 0x18
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#define REG_Rest2_Rate_Upper 0x19
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#define REG_Rest2_Downshift 0x1a
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#define REG_Rest3_Rate_Lower 0x1b
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#define REG_Rest3_Rate_Upper 0x1c
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#define REG_Observation 0x24
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#define REG_Data_Out_Lower 0x25
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#define REG_Data_Out_Upper 0x26
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#define REG_SROM_ID 0x2a
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#define REG_Min_SQ_Run 0x2b
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#define REG_RawData_Threshold 0x2c
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#define REG_Control2 0x2d
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#define REG_Config5_L 0x2e
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#define REG_Config5_H 0x2f
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#define REG_Power_Up_Reset 0X3a
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#define REG_Shutdown 0x3b
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#define REG_Inverse_Product_ID 0x3f
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#define REG_LiftCutoff_Cal3 0x41
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#define REG_Angle_Snap 0x42
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#define REG_LiftCutoff_Cal1 0x4a
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#define REG_Motion_Burst 0x50
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#define REG_SROM_Load_Burst 0x62
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#define REG_Lift_Config 0x63
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#define REG_RawData_Burst 0x64
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#define REG_LiftCutoff_Cal2 0x65
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#define REG_LiftCutoff_Cal_Timeout 0x71
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#define REG_LiftCutoff_Cal_Min_Length 0x72
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#define REG_PWM_Period_Cnt 0x73
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#define REG_PWM_Width_Cnt 0x74
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#define CPI_STEP 50
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// clang-format on
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// limits to 0--319, resulting in a CPI range of 50 -- 16000 (as only steps of 50 are possible).
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#ifndef MAX_CPI
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# define MAX_CPI 0x013f
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#endif
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bool _inBurst = false;
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#ifdef CONSOLE_ENABLE
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void print_byte(uint8_t byte) {
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dprintf("%c%c%c%c%c%c%c%c|", (byte & 0x80 ? '1' : '0'), (byte & 0x40 ? '1' : '0'), (byte & 0x20 ? '1' : '0'), (byte & 0x10 ? '1' : '0'), (byte & 0x08 ? '1' : '0'), (byte & 0x04 ? '1' : '0'), (byte & 0x02 ? '1' : '0'), (byte & 0x01 ? '1' : '0'));
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}
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#endif
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#define constrain(amt, low, high) ((amt) < (low) ? (low) : ((amt) > (high) ? (high) : (amt)))
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bool pmw3389_spi_start(void) {
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bool status = spi_start(PMW3389_CS_PIN, PMW3389_SPI_LSBFIRST, PMW3389_SPI_MODE, PMW3389_SPI_DIVISOR);
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// tNCS-SCLK, 120ns
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wait_us(1);
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return status;
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}
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spi_status_t pmw3389_write(uint8_t reg_addr, uint8_t data) {
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pmw3389_spi_start();
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if (reg_addr != REG_Motion_Burst) {
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_inBurst = false;
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}
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// send address of the register, with MSBit = 1 to indicate it's a write
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spi_status_t status = spi_write(reg_addr | 0x80);
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status = spi_write(data);
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// tSCLK-NCS for write operation is 35 us
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wait_us(35);
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spi_stop();
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// tSWW/tSWR (=180us) minus tSCLK-NCS. Could be shortened, but is looks like a safe lower bound
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wait_us(145);
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return status;
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}
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uint8_t pmw3389_read(uint8_t reg_addr) {
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pmw3389_spi_start();
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// send adress of the register, with MSBit = 0 to indicate it's a read
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spi_write(reg_addr & 0x7f);
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// tSRAD (=160us)
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wait_us(160);
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uint8_t data = spi_read();
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// tSCLK-NCS, 120ns
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wait_us(1);
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spi_stop();
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// tSRW/tSRR (=20us) minus tSCLK-NCS
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wait_us(19);
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return data;
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}
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bool pmw3389_init(void) {
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setPinOutput(PMW3389_CS_PIN);
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spi_init();
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_inBurst = false;
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spi_stop();
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pmw3389_spi_start();
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spi_stop();
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pmw3389_write(REG_Shutdown, 0xb6); // Shutdown first
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wait_ms(300);
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pmw3389_spi_start();
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wait_us(40);
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spi_stop();
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wait_us(40);
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// power up, need to first drive NCS high then low, see above.
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pmw3389_write(REG_Power_Up_Reset, 0x5a);
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wait_ms(50);
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// read registers and discard
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pmw3389_read(REG_Motion);
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pmw3389_read(REG_Delta_X_L);
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pmw3389_read(REG_Delta_X_H);
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pmw3389_read(REG_Delta_Y_L);
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pmw3389_read(REG_Delta_Y_H);
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pmw3389_upload_firmware();
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spi_stop();
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wait_ms(10);
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pmw3389_set_cpi(PMW3389_CPI);
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wait_ms(1);
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pmw3389_write(REG_Config2, 0x00);
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pmw3389_write(REG_Angle_Tune, constrain(ROTATIONAL_TRANSFORM_ANGLE, -127, 127));
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pmw3389_write(REG_Lift_Config, PMW3389_LIFTOFF_DISTANCE);
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bool init_success = pmw3389_check_signature();
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#ifdef CONSOLE_ENABLE
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if (init_success) {
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dprintf("pmw3389 signature verified");
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} else {
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dprintf("pmw3389 signature verification failed!");
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}
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#endif
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writePinLow(PMW3389_CS_PIN);
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return init_success;
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}
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void pmw3389_upload_firmware(void) {
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// Datasheet claims we need to disable REST mode first, but during startup
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// it's already disabled and we're not turning it on ...
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// pmw3389_write(REG_Config2, 0x00); // disable REST mode
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pmw3389_write(REG_SROM_Enable, 0x1d);
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wait_ms(10);
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pmw3389_write(REG_SROM_Enable, 0x18);
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pmw3389_spi_start();
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spi_write(REG_SROM_Load_Burst | 0x80);
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wait_us(15);
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for (uint16_t i = 0; i < FIRMWARE_LENGTH; i++) {
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spi_write(pgm_read_byte(firmware_data + i));
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#ifndef PMW3389_FIRMWARE_UPLOAD_FAST
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wait_us(15);
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#endif
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}
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wait_us(200);
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pmw3389_read(REG_SROM_ID);
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pmw3389_write(REG_Config2, 0x00);
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}
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bool pmw3389_check_signature(void) {
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uint8_t pid = pmw3389_read(REG_Product_ID);
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uint8_t iv_pid = pmw3389_read(REG_Inverse_Product_ID);
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uint8_t SROM_ver = pmw3389_read(REG_SROM_ID);
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return (pid == firmware_signature[0] && iv_pid == firmware_signature[1] && SROM_ver == firmware_signature[2]); // signature for SROM 0x04
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}
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uint16_t pmw3389_get_cpi(void) {
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uint16_t cpival = (pmw3389_read(REG_Resolution_H) << 8) | pmw3389_read(REG_Resolution_L);
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return (uint16_t)((cpival + 1) & 0xffff) * CPI_STEP;
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}
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void pmw3389_set_cpi(uint16_t cpi) {
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uint16_t cpival = constrain((cpi / CPI_STEP) - 1, 0, MAX_CPI);
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// Sets upper byte first for more consistent setting of cpi
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pmw3389_write(REG_Resolution_H, (cpival >> 8) & 0xff);
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pmw3389_write(REG_Resolution_L, cpival & 0xff);
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}
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report_pmw3389_t pmw3389_read_burst(void) {
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report_pmw3389_t report = {0};
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if (!_inBurst) {
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#ifdef CONSOLE_ENABLE
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dprintf("burst on");
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#endif
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pmw3389_write(REG_Motion_Burst, 0x00);
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_inBurst = true;
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}
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pmw3389_spi_start();
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spi_write(REG_Motion_Burst);
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wait_us(35); // waits for tSRAD_MOTBR
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report.motion = spi_read();
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spi_read(); // skip Observation
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// delta registers
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report.dx = spi_read();
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report.mdx = spi_read();
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report.dy = spi_read();
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report.mdy = spi_read();
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if (report.motion & 0b111) { // panic recovery, sometimes burst mode works weird.
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_inBurst = false;
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}
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spi_stop();
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#ifdef CONSOLE_ENABLE
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if (debug_mouse) {
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print_byte(report.motion);
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print_byte(report.dx);
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print_byte(report.mdx);
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print_byte(report.dy);
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print_byte(report.mdy);
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dprintf("\n");
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}
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#endif
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report.isMotion = (report.motion & 0x80) != 0;
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report.isOnSurface = (report.motion & 0x08) == 0;
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report.dx |= (report.mdx << 8);
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report.dx = report.dx * -1;
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report.dy |= (report.mdy << 8);
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report.dy = report.dy * -1;
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return report;
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}
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