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298 lines
8.0 KiB
298 lines
8.0 KiB
/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */
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/*
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Part of the Wiring project - http://wiring.uniandes.edu.co
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Copyright (c) 2004-05 Hernando Barragan
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General
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Public License along with this library; if not, write to the
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Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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Boston, MA 02111-1307 USA
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Modified 24 November 2006 by David A. Mellis
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Modified 1 August 2010 by Mark Sproul
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*/
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#include <inttypes.h>
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include <avr/pgmspace.h>
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#include <stdio.h>
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#include "wiring_private.h"
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static volatile voidFuncPtr intFunc[EXTERNAL_NUM_INTERRUPTS];
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// volatile static voidFuncPtr twiIntFunc;
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void attachInterrupt(uint8_t interruptNum, void (*userFunc)(void), int mode) {
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if(interruptNum < EXTERNAL_NUM_INTERRUPTS) {
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intFunc[interruptNum] = userFunc;
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// Configure the interrupt mode (trigger on low input, any change, rising
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// edge, or falling edge). The mode constants were chosen to correspond
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// to the configuration bits in the hardware register, so we simply shift
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// the mode into place.
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// Enable the interrupt.
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switch (interruptNum) {
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#if defined(__AVR_ATmega32U4__)
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// I hate doing this, but the register assignment differs between the 1280/2560
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// and the 32U4. Since avrlib defines registers PCMSK1 and PCMSK2 that aren't
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// even present on the 32U4 this is the only way to distinguish between them.
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case 0:
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EICRA = (EICRA & ~((1<<ISC00) | (1<<ISC01))) | (mode << ISC00);
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EIMSK |= (1<<INT0);
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break;
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case 1:
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EICRA = (EICRA & ~((1<<ISC10) | (1<<ISC11))) | (mode << ISC10);
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EIMSK |= (1<<INT1);
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break;
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#elif defined(EICRA) && defined(EICRB) && defined(EIMSK)
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case 2:
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EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
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EIMSK |= (1 << INT0);
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break;
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case 3:
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EICRA = (EICRA & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
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EIMSK |= (1 << INT1);
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break;
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case 4:
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EICRA = (EICRA & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
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EIMSK |= (1 << INT2);
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break;
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case 5:
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EICRA = (EICRA & ~((1 << ISC30) | (1 << ISC31))) | (mode << ISC30);
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EIMSK |= (1 << INT3);
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break;
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case 0:
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EICRB = (EICRB & ~((1 << ISC40) | (1 << ISC41))) | (mode << ISC40);
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EIMSK |= (1 << INT4);
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break;
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case 1:
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EICRB = (EICRB & ~((1 << ISC50) | (1 << ISC51))) | (mode << ISC50);
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EIMSK |= (1 << INT5);
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break;
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case 6:
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EICRB = (EICRB & ~((1 << ISC60) | (1 << ISC61))) | (mode << ISC60);
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EIMSK |= (1 << INT6);
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break;
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case 7:
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EICRB = (EICRB & ~((1 << ISC70) | (1 << ISC71))) | (mode << ISC70);
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EIMSK |= (1 << INT7);
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break;
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#else
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case 0:
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#if defined(EICRA) && defined(ISC00) && defined(EIMSK)
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EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
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EIMSK |= (1 << INT0);
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#elif defined(MCUCR) && defined(ISC00) && defined(GICR)
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MCUCR = (MCUCR & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
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GICR |= (1 << INT0);
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#elif defined(MCUCR) && defined(ISC00) && defined(GIMSK)
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MCUCR = (MCUCR & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
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GIMSK |= (1 << INT0);
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#else
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#error attachInterrupt not finished for this CPU (case 0)
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#endif
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break;
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case 1:
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#if defined(EICRA) && defined(ISC10) && defined(ISC11) && defined(EIMSK)
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EICRA = (EICRA & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
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EIMSK |= (1 << INT1);
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#elif defined(MCUCR) && defined(ISC10) && defined(ISC11) && defined(GICR)
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MCUCR = (MCUCR & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
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GICR |= (1 << INT1);
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#elif defined(MCUCR) && defined(ISC10) && defined(GIMSK) && defined(GIMSK)
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MCUCR = (MCUCR & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
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GIMSK |= (1 << INT1);
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#else
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#warning attachInterrupt may need some more work for this cpu (case 1)
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#endif
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break;
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case 2:
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#if defined(EICRA) && defined(ISC20) && defined(ISC21) && defined(EIMSK)
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EICRA = (EICRA & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
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EIMSK |= (1 << INT2);
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#elif defined(MCUCR) && defined(ISC20) && defined(ISC21) && defined(GICR)
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MCUCR = (MCUCR & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
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GICR |= (1 << INT2);
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#elif defined(MCUCR) && defined(ISC20) && defined(GIMSK) && defined(GIMSK)
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MCUCR = (MCUCR & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
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GIMSK |= (1 << INT2);
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#endif
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break;
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#endif
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}
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}
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}
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void detachInterrupt(uint8_t interruptNum) {
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if(interruptNum < EXTERNAL_NUM_INTERRUPTS) {
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// Disable the interrupt. (We can't assume that interruptNum is equal
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// to the number of the EIMSK bit to clear, as this isn't true on the
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// ATmega8. There, INT0 is 6 and INT1 is 7.)
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switch (interruptNum) {
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#if defined(__AVR_ATmega32U4__)
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case 0:
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EIMSK &= ~(1<<INT0);
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break;
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case 1:
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EIMSK &= ~(1<<INT1);
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break;
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#elif defined(EICRA) && defined(EICRB) && defined(EIMSK)
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case 2:
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EIMSK &= ~(1 << INT0);
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break;
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case 3:
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EIMSK &= ~(1 << INT1);
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break;
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case 4:
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EIMSK &= ~(1 << INT2);
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break;
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case 5:
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EIMSK &= ~(1 << INT3);
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break;
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case 0:
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EIMSK &= ~(1 << INT4);
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break;
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case 1:
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EIMSK &= ~(1 << INT5);
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break;
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case 6:
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EIMSK &= ~(1 << INT6);
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break;
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case 7:
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EIMSK &= ~(1 << INT7);
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break;
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#else
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case 0:
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#if defined(EIMSK) && defined(INT0)
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EIMSK &= ~(1 << INT0);
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#elif defined(GICR) && defined(ISC00)
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GICR &= ~(1 << INT0); // atmega32
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#elif defined(GIMSK) && defined(INT0)
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GIMSK &= ~(1 << INT0);
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#else
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#error detachInterrupt not finished for this cpu
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#endif
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break;
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case 1:
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#if defined(EIMSK) && defined(INT1)
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EIMSK &= ~(1 << INT1);
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#elif defined(GICR) && defined(INT1)
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GICR &= ~(1 << INT1); // atmega32
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#elif defined(GIMSK) && defined(INT1)
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GIMSK &= ~(1 << INT1);
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#else
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#warning detachInterrupt may need some more work for this cpu (case 1)
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#endif
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break;
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#endif
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}
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intFunc[interruptNum] = 0;
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}
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}
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/*
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void attachInterruptTwi(void (*userFunc)(void) ) {
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twiIntFunc = userFunc;
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}
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*/
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#if defined(__AVR_ATmega32U4__)
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SIGNAL(INT0_vect) {
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if(intFunc[EXTERNAL_INT_0])
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intFunc[EXTERNAL_INT_0]();
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}
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SIGNAL(INT1_vect) {
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if(intFunc[EXTERNAL_INT_1])
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intFunc[EXTERNAL_INT_1]();
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}
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#elif defined(EICRA) && defined(EICRB)
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SIGNAL(INT0_vect) {
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if(intFunc[EXTERNAL_INT_2])
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intFunc[EXTERNAL_INT_2]();
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}
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SIGNAL(INT1_vect) {
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if(intFunc[EXTERNAL_INT_3])
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intFunc[EXTERNAL_INT_3]();
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}
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SIGNAL(INT2_vect) {
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if(intFunc[EXTERNAL_INT_4])
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intFunc[EXTERNAL_INT_4]();
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}
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SIGNAL(INT3_vect) {
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if(intFunc[EXTERNAL_INT_5])
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intFunc[EXTERNAL_INT_5]();
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}
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SIGNAL(INT4_vect) {
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if(intFunc[EXTERNAL_INT_0])
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intFunc[EXTERNAL_INT_0]();
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}
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SIGNAL(INT5_vect) {
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if(intFunc[EXTERNAL_INT_1])
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intFunc[EXTERNAL_INT_1]();
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}
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SIGNAL(INT6_vect) {
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if(intFunc[EXTERNAL_INT_6])
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intFunc[EXTERNAL_INT_6]();
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}
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SIGNAL(INT7_vect) {
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if(intFunc[EXTERNAL_INT_7])
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intFunc[EXTERNAL_INT_7]();
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}
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#else
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SIGNAL(INT0_vect) {
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if(intFunc[EXTERNAL_INT_0])
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intFunc[EXTERNAL_INT_0]();
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}
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SIGNAL(INT1_vect) {
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if(intFunc[EXTERNAL_INT_1])
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intFunc[EXTERNAL_INT_1]();
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}
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#if defined(EICRA) && defined(ISC20)
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SIGNAL(INT2_vect) {
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if(intFunc[EXTERNAL_INT_2])
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intFunc[EXTERNAL_INT_2]();
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}
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#endif
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#endif
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/*
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SIGNAL(SIG_2WIRE_SERIAL) {
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if(twiIntFunc)
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twiIntFunc();
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}
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*/
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