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160 lines
6.6 KiB
160 lines
6.6 KiB
/*
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* LEDDriver.c
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*
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* Created on: Aug 26, 2013
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* Author: Omri Iluz
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*/
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#include "ws2812.h"
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#include "stdlib.h"
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static uint8_t *fb;
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static int sLeds;
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static stm32_gpio_t *sPort;
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static uint32_t sMask;
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uint8_t* dma_source;
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void setColor(uint8_t color, uint8_t *buf,uint32_t mask){
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int i;
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for (i=0;i<8;i++){
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buf[i]=((color<<i)&0b10000000?0x0:mask);
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}
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}
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void setColorRGB(Color c, uint8_t *buf, uint32_t mask){
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setColor(c.G,buf, mask);
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setColor(c.R,buf+8, mask);
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setColor(c.B,buf+16, mask);
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}
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/**
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* @brief Initialize Led Driver
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* @details Initialize the Led Driver based on parameters.
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* Following initialization, the frame buffer would automatically be
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* exported to the supplied port and pins in the right timing to drive
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* a chain of WS2812B controllers
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* @note The function assumes the controller is running at 72Mhz
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* @note Timing is critical for WS2812. While all timing is done in hardware
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* need to verify memory bandwidth is not exhausted to avoid DMA delays
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*
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* @param[in] leds length of the LED chain controlled by each pin
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* @param[in] port which port would be used for output
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* @param[in] mask Which pins would be used for output, each pin is a full chain
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* @param[out] o_fb initialized frame buffer
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*
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*/
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void ledDriverInit(int leds, stm32_gpio_t *port, uint32_t mask, uint8_t **o_fb) {
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sLeds=leds;
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sPort=port;
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sMask=mask;
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palSetGroupMode(port, sMask, 0, PAL_MODE_OUTPUT_PUSHPULL|PAL_STM32_OSPEED_HIGHEST|PAL_STM32_PUPDR_FLOATING);
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// configure pwm timers -
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// timer 2 as master, active for data transmission and inactive to disable transmission during reset period (50uS)
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// timer 3 as slave, during active time creates a 1.25 uS signal, with duty cycle controlled by frame buffer values
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static PWMConfig pwmc2 = {72000000 / 90, /* 800Khz PWM clock frequency. 1/90 of PWMC3 */
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(72000000 / 90) * 0.05, /*Total period is 50ms (20FPS), including sLeds cycles + reset length for ws2812b and FB writes */
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NULL,
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{ {PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_DISABLED, NULL},
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{PWM_OUTPUT_DISABLED, NULL},
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{PWM_OUTPUT_DISABLED, NULL}},
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TIM_CR2_MMS_2, /* master mode selection */
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0, };
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/* master mode selection */
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static PWMConfig pwmc3 = {72000000,/* 72Mhz PWM clock frequency. */
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90, /* 90 cycles period (1.25 uS per period @72Mhz */
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NULL,
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{ {PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL}},
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0,
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0,
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};
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dma_source = chHeapAlloc(NULL, 1);
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fb = chHeapAlloc(NULL, ((sLeds) * 24)+10);
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*o_fb=fb;
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int j;
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for (j = 0; j < (sLeds) * 24; j++) fb[j] = 0;
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dma_source[0] = sMask;
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// DMA stream 2, triggered by channel3 pwm signal. if FB indicates, reset output value early to indicate "0" bit to ws2812
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dmaStreamAllocate(STM32_DMA1_STREAM2, 10, NULL, NULL);
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dmaStreamSetPeripheral(STM32_DMA1_STREAM2, &(sPort->BSRR.H.clear));
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dmaStreamSetMemory0(STM32_DMA1_STREAM2, fb);
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dmaStreamSetTransactionSize(STM32_DMA1_STREAM2, (sLeds) * 24);
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dmaStreamSetMode(
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STM32_DMA1_STREAM2,
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STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_MINC | STM32_DMA_CR_PSIZE_BYTE
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| STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_CIRC | STM32_DMA_CR_PL(2));
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// DMA stream 3, triggered by pwm update event. output high at beginning of signal
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dmaStreamAllocate(STM32_DMA1_STREAM3, 10, NULL, NULL);
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dmaStreamSetPeripheral(STM32_DMA1_STREAM3, &(sPort->BSRR.H.set));
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dmaStreamSetMemory0(STM32_DMA1_STREAM3, dma_source);
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dmaStreamSetTransactionSize(STM32_DMA1_STREAM3, 1);
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dmaStreamSetMode(
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STM32_DMA1_STREAM3, STM32_DMA_CR_TEIE|
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STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_BYTE
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| STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_CIRC | STM32_DMA_CR_PL(3));
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// DMA stream 6, triggered by channel1 update event. reset output value late to indicate "1" bit to ws2812.
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// always triggers but no affect if dma stream 2 already change output value to 0
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dmaStreamAllocate(STM32_DMA1_STREAM6, 10, NULL, NULL);
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dmaStreamSetPeripheral(STM32_DMA1_STREAM6, &(sPort->BSRR.H.clear));
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dmaStreamSetMemory0(STM32_DMA1_STREAM6, dma_source);
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dmaStreamSetTransactionSize(STM32_DMA1_STREAM6, 1);
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dmaStreamSetMode(
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STM32_DMA1_STREAM6,
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STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_BYTE
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| STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_CIRC | STM32_DMA_CR_PL(3));
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pwmStart(&PWMD2, &pwmc2);
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pwmStart(&PWMD3, &pwmc3);
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// set pwm3 as slave, triggerd by pwm2 oc1 event. disables pwmd2 for synchronization.
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PWMD3.tim->SMCR |= TIM_SMCR_SMS_0 | TIM_SMCR_SMS_2 | TIM_SMCR_TS_0;
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PWMD2.tim->CR1 &= ~TIM_CR1_CEN;
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// set pwm values.
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// 28 (duty in ticks) / 90 (period in ticks) * 1.25uS (period in S) = 0.39 uS
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pwmEnableChannel(&PWMD3, 2, 28);
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// 58 (duty in ticks) / 90 (period in ticks) * 1.25uS (period in S) = 0.806 uS
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pwmEnableChannel(&PWMD3, 0, 58);
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// active during transfer of 90 cycles * sLeds * 24 bytes * 1/90 multiplier
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pwmEnableChannel(&PWMD2, 0, 90 * sLeds * 24 / 90);
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// stop and reset counters for synchronization
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PWMD2.tim->CNT = 0;
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// Slave (TIM3) needs to "update" immediately after master (TIM2) start in order to start in sync.
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// this initial sync is crucial for the stability of the run
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PWMD3.tim->CNT = 89;
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PWMD3.tim->DIER |= TIM_DIER_CC3DE | TIM_DIER_CC1DE | TIM_DIER_UDE;
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dmaStreamEnable(STM32_DMA1_STREAM3);
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dmaStreamEnable(STM32_DMA1_STREAM6);
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dmaStreamEnable(STM32_DMA1_STREAM2);
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// all systems go! both timers and all channels are configured to resonate
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// in complete sync without any need for CPU cycles (only DMA and timers)
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// start pwm2 for system to start resonating
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PWMD2.tim->CR1 |= TIM_CR1_CEN;
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}
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void ledDriverWaitCycle(void){
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while (PWMD2.tim->CNT < 90 * sLeds * 24 / 90){chThdSleepMicroseconds(1);};
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}
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void testPatternFB(uint8_t *fb){
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int i;
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Color tmpC = {rand()%256, rand()%256, rand()%256};
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for (i=0;i<sLeds;i++){
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setColorRGB(tmpC,fb+24*i, sMask);
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}
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}
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void ws2812_setleds(LED_TYPE *ledarray, uint16_t number_of_leds) {
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// uint8_t i = 0;
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// while (i < number_of_leds) {
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// ws2812_write_led(i, ledarray[i].r, ledarray[i].g, ledarray[i].b);
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// i++;
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// }
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}
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void ws2812_setleds_rgbw(LED_TYPE *ledarray, uint16_t number_of_leds) {
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}
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