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457 lines
15 KiB
457 lines
15 KiB
// Copyright 2022 Stefan Kerkmann
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "quantum.h"
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#include "serial_usart.h"
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#include "serial_protocol.h"
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#include "hardware/pio.h"
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#include "hardware/clocks.h"
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#if !defined(MCU_RP)
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# error PIO Driver is only available for Raspberry Pi 2040 MCUs!
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#endif
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static inline bool receive_impl(uint8_t* destination, const size_t size, sysinterval_t timeout);
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static inline bool send_impl(const uint8_t* source, const size_t size);
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static inline void pio_serve_interrupt(void);
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#define MSG_PIO_ERROR ((msg_t)(-3))
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#if defined(SERIAL_PIO_USE_PIO1)
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static const PIO pio = pio1;
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OSAL_IRQ_HANDLER(RP_PIO1_IRQ_0_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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pio_serve_interrupt();
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OSAL_IRQ_EPILOGUE();
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}
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#else
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static const PIO pio = pio0;
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OSAL_IRQ_HANDLER(RP_PIO0_IRQ_0_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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pio_serve_interrupt();
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#define UART_TX_WRAP_TARGET 0
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#define UART_TX_WRAP 3
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// clang-format off
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#if defined(SERIAL_USART_FULL_DUPLEX)
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static const uint16_t uart_tx_program_instructions[] = {
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// .wrap_target
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0x9fa0, // 0: pull block side 1 [7]
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0xf727, // 1: set x, 7 side 0 [7]
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0x6001, // 2: out pins, 1
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0x0642, // 3: jmp x--, 2 [6]
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// .wrap
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};
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#else
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static const uint16_t uart_tx_program_instructions[] = {
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// .wrap_target
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0x9fa0, // 0: pull block side 1 [7]
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0xf727, // 1: set x, 7 side 0 [7]
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0x6081, // 2: out pindirs, 1
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0x0642, // 3: jmp x--, 2 [6]
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// .wrap
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};
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#endif
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// clang-format on
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static const pio_program_t uart_tx_program = {
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.instructions = uart_tx_program_instructions,
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.length = 4,
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.origin = -1,
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};
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#define UART_RX_WRAP_TARGET 0
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#define UART_RX_WRAP 8
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// clang-format off
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static const uint16_t uart_rx_program_instructions[] = {
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// .wrap_target
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0x2020, // 0: wait 0 pin, 0
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0xea27, // 1: set x, 7 [10]
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0x4001, // 2: in pins, 1
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0x0642, // 3: jmp x--, 2 [6]
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0x00c8, // 4: jmp pin, 8
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0xc020, // 5: irq wait 0
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0x20a0, // 6: wait 1 pin, 0
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0x0000, // 7: jmp 0
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0x8020, // 8: push block
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// .wrap
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};
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// clang-format on
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static const pio_program_t uart_rx_program = {
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.instructions = uart_rx_program_instructions,
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.length = 9,
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.origin = -1,
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};
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thread_reference_t rx_thread = NULL;
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static int rx_state_machine = -1;
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thread_reference_t tx_thread = NULL;
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static int tx_state_machine = -1;
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void pio_serve_interrupt(void) {
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uint32_t irqs = pio->ints0;
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// The RX FIFO is not empty any more, therefore wake any sleeping rx thread
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if (irqs & (PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS << rx_state_machine)) {
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// Disable rx not empty interrupt
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pio_set_irq0_source_enabled(pio, pis_sm0_rx_fifo_not_empty + rx_state_machine, false);
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osalSysLockFromISR();
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osalThreadResumeI(&rx_thread, MSG_OK);
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osalSysUnlockFromISR();
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}
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// The TX FIFO is not full any more, therefore wake any sleeping tx thread
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if (irqs & (PIO_IRQ0_INTF_SM0_TXNFULL_BITS << tx_state_machine)) {
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// Disable tx not full interrupt
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pio_set_irq0_source_enabled(pio, pis_sm0_tx_fifo_not_full + tx_state_machine, false);
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osalSysLockFromISR();
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osalThreadResumeI(&tx_thread, MSG_OK);
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osalSysUnlockFromISR();
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}
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// IRQ 0 is set on framing or break errors by the rx state machine
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if (pio_interrupt_get(pio, 0UL)) {
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pio_interrupt_clear(pio, 0UL);
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osalSysLockFromISR();
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osalThreadResumeI(&rx_thread, MSG_PIO_ERROR);
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osalSysUnlockFromISR();
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}
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}
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#if !defined(SERIAL_USART_FULL_DUPLEX)
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// The internal pull-ups of the RP2040 are rather weakish with a range of 50k to
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// 80k, which in turn do not provide enough current to guarantee fast signal rise
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// times with a parasitic capacitance of greater than 100pf. In real world
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// applications, like split keyboards which might have vias in the signal path
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// or long PCB traces, this prevents a successful communication. The solution
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// is to temporarily augment the weak pull ups from the receiving side by
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// driving the tx pin high. On the receiving side the lowest possible drive
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// strength is chosen because the transmitting side must still be able to drive
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// the signal low. With this configuration the rise times are fast enough and
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// the generated low level with 360mV will generate a logical zero.
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static inline void enter_rx_state(void) {
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osalSysLock();
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// Wait for the transmitting state machines FIFO to run empty. At this point
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// the last byte has been pulled from the transmitting state machines FIFO
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// into the output shift register. We have to wait a tiny bit more until
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// this byte is transmitted, before we can turn on the receiving state
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// machine again.
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while (!pio_sm_is_tx_fifo_empty(pio, tx_state_machine)) {
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}
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// Wait for ~11 bits, 1 start bit + 8 data bits + 1 stop bit + 1 bit
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// headroom.
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chSysPolledDelayX(US2RTC(1 * MHZ, (1000000U * 11 / SERIAL_USART_SPEED)));
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// Disable tx state machine to not interfere with our tx pin manipulation
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pio_sm_set_enabled(pio, tx_state_machine, false);
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gpio_set_drive_strength(SERIAL_USART_TX_PIN, GPIO_DRIVE_STRENGTH_2MA);
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pio_sm_set_pins_with_mask(pio, tx_state_machine, 1U << SERIAL_USART_TX_PIN, 1U << SERIAL_USART_TX_PIN);
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pio_sm_set_consecutive_pindirs(pio, tx_state_machine, SERIAL_USART_TX_PIN, 1U, false);
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pio_sm_set_enabled(pio, rx_state_machine, true);
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osalSysUnlock();
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}
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static inline void leave_rx_state(void) {
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osalSysLock();
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// In Half-duplex operation the tx pin dual-functions as sender and
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// receiver. To not receive the data we will send, we disable the receiving
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// state machine.
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pio_sm_set_enabled(pio, rx_state_machine, false);
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pio_sm_set_consecutive_pindirs(pio, tx_state_machine, SERIAL_USART_TX_PIN, 1U, true);
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pio_sm_set_pins_with_mask(pio, tx_state_machine, 0U, 1U << SERIAL_USART_TX_PIN);
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gpio_set_drive_strength(SERIAL_USART_TX_PIN, GPIO_DRIVE_STRENGTH_12MA);
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pio_sm_restart(pio, tx_state_machine);
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pio_sm_set_enabled(pio, tx_state_machine, true);
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osalSysUnlock();
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}
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#else
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// All this trickery is gladly not necessary for full-duplex.
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static inline void enter_rx_state(void) {}
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static inline void leave_rx_state(void) {}
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#endif
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/**
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* @brief Clear the RX and TX hardware FIFOs of the state machines.
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*/
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inline void serial_transport_driver_clear(void) {
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osalSysLock();
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pio_sm_clear_fifos(pio, rx_state_machine);
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pio_sm_clear_fifos(pio, tx_state_machine);
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osalSysUnlock();
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}
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static inline msg_t sync_tx(sysinterval_t timeout) {
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msg_t msg = MSG_OK;
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osalSysLock();
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while (pio_sm_is_tx_fifo_full(pio, tx_state_machine)) {
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pio_set_irq0_source_enabled(pio, pis_sm0_tx_fifo_not_full + tx_state_machine, true);
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msg = osalThreadSuspendTimeoutS(&tx_thread, timeout);
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if (msg < MSG_OK) {
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break;
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}
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}
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osalSysUnlock();
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return msg;
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}
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static inline bool send_impl(const uint8_t* source, const size_t size) {
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size_t send = 0;
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msg_t msg;
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while (send < size) {
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msg = sync_tx(TIME_MS2I(SERIAL_USART_TIMEOUT));
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if (msg < MSG_OK) {
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return false;
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}
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osalSysLock();
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while (send < size) {
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if (pio_sm_is_tx_fifo_full(pio, tx_state_machine)) {
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break;
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}
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if (send >= size) {
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break;
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}
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pio_sm_put(pio, tx_state_machine, (uint32_t)(*source));
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source++;
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send++;
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}
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osalSysUnlock();
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}
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return send == size;
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}
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/**
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* @brief Blocking send of buffer with timeout.
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*
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* @return true Send success.
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* @return false Send failed.
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*/
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inline bool serial_transport_send(const uint8_t* source, const size_t size) {
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leave_rx_state();
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bool result = send_impl(source, size);
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enter_rx_state();
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return result;
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}
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static inline msg_t sync_rx(sysinterval_t timeout) {
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msg_t msg = MSG_OK;
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osalSysLock();
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while (pio_sm_is_rx_fifo_empty(pio, rx_state_machine)) {
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pio_set_irq0_source_enabled(pio, pis_sm0_rx_fifo_not_empty + rx_state_machine, true);
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msg = osalThreadSuspendTimeoutS(&rx_thread, timeout);
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if (msg < MSG_OK) {
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break;
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}
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}
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osalSysUnlock();
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return msg;
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}
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static inline bool receive_impl(uint8_t* destination, const size_t size, sysinterval_t timeout) {
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size_t read = 0U;
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while (read < size) {
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msg_t msg = sync_rx(timeout);
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if (msg < MSG_OK) {
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return false;
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}
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osalSysLock();
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while (true) {
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if (pio_sm_is_rx_fifo_empty(pio, rx_state_machine)) {
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break;
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}
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if (read >= size) {
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break;
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}
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*destination++ = *((uint8_t*)&pio->rxf[rx_state_machine] + 3U);
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read++;
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}
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osalSysUnlock();
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}
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return read == size;
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}
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/**
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* @brief Blocking receive of size * bytes with timeout.
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*
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* @return true Receive success.
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* @return false Receive failed, e.g. by timeout.
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*/
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inline bool serial_transport_receive(uint8_t* destination, const size_t size) {
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return receive_impl(destination, size, TIME_MS2I(SERIAL_USART_TIMEOUT));
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}
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/**
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* @brief Blocking receive of size * bytes.
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*
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* @return true Receive success.
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* @return false Receive failed.
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*/
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inline bool serial_transport_receive_blocking(uint8_t* destination, const size_t size) {
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return receive_impl(destination, size, TIME_INFINITE);
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}
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static inline void pio_tx_init(pin_t tx_pin) {
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uint pio_idx = pio_get_index(pio);
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uint offset = pio_add_program(pio, &uart_tx_program);
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#if defined(SERIAL_USART_FULL_DUPLEX)
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// clang-format off
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iomode_t tx_pin_mode = PAL_RP_GPIO_OE |
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PAL_RP_PAD_SLEWFAST |
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PAL_RP_PAD_DRIVE4 |
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(pio_idx == 0 ? PAL_MODE_ALTERNATE_PIO0 : PAL_MODE_ALTERNATE_PIO1);
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// clang-format on
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pio_sm_set_pins_with_mask(pio, tx_state_machine, 1U << tx_pin, 1U << tx_pin);
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pio_sm_set_consecutive_pindirs(pio, tx_state_machine, tx_pin, 1U, true);
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#else
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// clang-format off
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iomode_t tx_pin_mode = PAL_RP_PAD_IE |
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PAL_RP_GPIO_OE |
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PAL_RP_PAD_SCHMITT |
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PAL_RP_PAD_PUE |
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PAL_RP_PAD_SLEWFAST |
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PAL_RP_PAD_DRIVE12 |
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PAL_RP_IOCTRL_OEOVER_DRVINVPERI |
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(pio_idx == 0 ? PAL_MODE_ALTERNATE_PIO0 : PAL_MODE_ALTERNATE_PIO1);
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// clang-format on
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pio_sm_set_pins_with_mask(pio, tx_state_machine, 0U << tx_pin, 1U << tx_pin);
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pio_sm_set_consecutive_pindirs(pio, tx_state_machine, tx_pin, 1U, true);
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#endif
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palSetLineMode(tx_pin, tx_pin_mode);
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pio_sm_config config = pio_get_default_sm_config();
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sm_config_set_wrap(&config, offset + UART_TX_WRAP_TARGET, offset + UART_TX_WRAP);
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#if defined(SERIAL_USART_FULL_DUPLEX)
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sm_config_set_sideset(&config, 2, true, false);
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#else
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sm_config_set_sideset(&config, 2, true, true);
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#endif
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// OUT shifts to right, no autopull
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sm_config_set_out_shift(&config, true, false, 32);
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// We are mapping both OUT and side-set to the same pin, because sometimes
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// we need to assert user data onto the pin (with OUT) and sometimes
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// assert constant values (start/stop bit)
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sm_config_set_out_pins(&config, tx_pin, 1);
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sm_config_set_sideset_pins(&config, tx_pin);
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// We only need TX, so get an 8-deep FIFO!
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sm_config_set_fifo_join(&config, PIO_FIFO_JOIN_TX);
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// SM transmits 1 bit per 8 execution cycles.
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float div = (float)clock_get_hz(clk_sys) / (8 * SERIAL_USART_SPEED);
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sm_config_set_clkdiv(&config, div);
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pio_sm_init(pio, tx_state_machine, offset, &config);
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pio_sm_set_enabled(pio, tx_state_machine, true);
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}
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static inline void pio_rx_init(pin_t rx_pin) {
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uint offset = pio_add_program(pio, &uart_rx_program);
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#if defined(SERIAL_USART_FULL_DUPLEX)
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uint pio_idx = pio_get_index(pio);
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pio_sm_set_consecutive_pindirs(pio, rx_state_machine, rx_pin, 1, false);
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// clang-format off
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iomode_t rx_pin_mode = PAL_RP_PAD_IE |
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PAL_RP_PAD_SCHMITT |
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PAL_RP_PAD_PUE |
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(pio_idx == 0 ? PAL_MODE_ALTERNATE_PIO0 : PAL_MODE_ALTERNATE_PIO1);
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// clang-format on
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palSetLineMode(rx_pin, rx_pin_mode);
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#endif
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pio_sm_config config = pio_get_default_sm_config();
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sm_config_set_wrap(&config, offset + UART_RX_WRAP_TARGET, offset + UART_RX_WRAP);
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sm_config_set_in_pins(&config, rx_pin); // for WAIT, IN
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sm_config_set_jmp_pin(&config, rx_pin); // for JMP
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// Shift to right, autopush disabled
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sm_config_set_in_shift(&config, true, false, 32);
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// Deeper FIFO as we're not doing any TX
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sm_config_set_fifo_join(&config, PIO_FIFO_JOIN_RX);
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// SM transmits 1 bit per 8 execution cycles.
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float div = (float)clock_get_hz(clk_sys) / (8 * SERIAL_USART_SPEED);
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sm_config_set_clkdiv(&config, div);
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pio_sm_init(pio, rx_state_machine, offset, &config);
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pio_sm_set_enabled(pio, rx_state_machine, true);
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}
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static inline void pio_init(pin_t tx_pin, pin_t rx_pin) {
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uint pio_idx = pio_get_index(pio);
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/* Get PIOx peripheral out of reset state. */
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hal_lld_peripheral_unreset(pio_idx == 0 ? RESETS_ALLREG_PIO0 : RESETS_ALLREG_PIO1);
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tx_state_machine = pio_claim_unused_sm(pio, true);
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if (tx_state_machine < 0) {
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dprintln("ERROR: Failed to acquire state machine for serial transmission!");
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return;
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}
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pio_tx_init(tx_pin);
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rx_state_machine = pio_claim_unused_sm(pio, true);
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if (rx_state_machine < 0) {
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dprintln("ERROR: Failed to acquire state machine for serial reception!");
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return;
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}
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pio_rx_init(rx_pin);
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// Enable error flag IRQ source for rx state machine
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pio_set_irq0_source_enabled(pio, pis_sm0_rx_fifo_not_empty + rx_state_machine, true);
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pio_set_irq0_source_enabled(pio, pis_sm0_tx_fifo_not_full + tx_state_machine, true);
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pio_set_irq0_source_enabled(pio, pis_interrupt0, true);
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// Enable PIO specific interrupt vector
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#if defined(SERIAL_PIO_USE_PIO1)
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nvicEnableVector(RP_PIO1_IRQ_0_NUMBER, RP_IRQ_UART0_PRIORITY);
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#else
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nvicEnableVector(RP_PIO0_IRQ_0_NUMBER, RP_IRQ_UART0_PRIORITY);
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#endif
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enter_rx_state();
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}
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/**
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* @brief PIO driver specific initialization function for the master side.
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*/
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void serial_transport_driver_master_init(void) {
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#if defined(SERIAL_USART_FULL_DUPLEX)
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pin_t tx_pin = SERIAL_USART_TX_PIN;
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pin_t rx_pin = SERIAL_USART_RX_PIN;
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#else
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pin_t tx_pin = SERIAL_USART_TX_PIN;
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pin_t rx_pin = SERIAL_USART_TX_PIN;
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#endif
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#if defined(SERIAL_USART_PIN_SWAP)
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pio_init(rx_pin, tx_pin);
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#else
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pio_init(tx_pin, rx_pin);
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#endif
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}
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/**
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* @brief PIO driver specific initialization function for the slave side.
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*/
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void serial_transport_driver_slave_init(void) {
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#if defined(SERIAL_USART_FULL_DUPLEX)
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pin_t tx_pin = SERIAL_USART_TX_PIN;
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pin_t rx_pin = SERIAL_USART_RX_PIN;
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#else
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pin_t tx_pin = SERIAL_USART_TX_PIN;
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pin_t rx_pin = SERIAL_USART_TX_PIN;
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#endif
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pio_init(tx_pin, rx_pin);
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}
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