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  1. # coreboot-x230
  2. pre-built coreboot images and documentation on how to flash them for the Thinkpad X230
  3. These imges:
  4. * include Lenovo's proprietary VGA BIOS ROM. If it might not be needed anymore, I'm happy for hints.
  5. * include [SeaBIOS](https://seabios.org/SeaBIOS) as coreboot payload, for maximum compatibility.
  6. * are meant to be [flashed externally](#how-to-flash)
  7. ## Latest build
  8. See our [releases](https://github.com/merge/coreboot-x230/releases)
  9. ## Flashing for the first time
  10. ### EC firmware
  11. Enter Lenovo's BIOS with __F1__ and check the embedded controller (EC) version to be
  12. __1.14__ and upgrade using [the latest bootable CD](https://support.lenovo.com/at/en/downloads/ds029188)
  13. if it isn't. The EC cannot be upgraded when coreboot is installed. (In case a newer
  14. version should ever be available (I doubt it), you could temporarily flash back your
  15. original Lenovo BIOS image)
  16. ### me_cleaner
  17. The Intel Management Engine resides on the 8MB chip. We don't need to touch it
  18. for coreboot-upgrades in the future, but while opening up the Thinkpad anyways,
  19. we can save it and run [ifdtool](https://github.com/coreboot/coreboot/tree/master/util/ifdtool)
  20. and [me_cleaner](https://github.com/corna/me_cleaner) on it:
  21. flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=128 -c "MX25L3206E/MX25L3208E" -r ifdmegbe.rom
  22. flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=128 -c "MX25L3206E/MX25L3208E" -r ifdmegbe2.rom
  23. diff ifdmegbe.rom ifdmegbe2.rom
  24. git clone https://github.com/corna/me_cleaner.git && cd me_cleaner
  25. ./me_cleaner.py -O ifdmegbe_meclean.rom ifdmegbe.rom
  26. ifdtool -u ifdmegbe_meclean.rom
  27. flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=128 -c "MX25L3206E/MX25L3208E" -w ifdmegbe_meclean.rom.new
  28. ### save the 4MB chip
  29. (internally, memory of the two chips is mapped together, the 8MB being the lower
  30. part, but we can essientially ignore that)
  31. For the first time, we have to save the original image, just like we did with
  32. the 8MB chip above:
  33. flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=128 -r top1.rom
  34. flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=128 -r top2.rom
  35. diff top1.rom top2.rom
  36. ## Flashing the coreboot / SeaBIOS image
  37. When __upgrading__ to a new version, for example when a new [SeaBIOS](https://seabios.org/Releases)
  38. version is available, only this has to be done.
  39. Download the latest release image we provide here and flash it:
  40. flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=128 -w x230_coreboot_seabios_example_top.rom
  41. ## How to flash
  42. We flash externally, using a "Pomona 5250 8-pin SOIC test clip". You'll find
  43. one easily.
  44. We connect it to a Raspberry Pi 3, running [Raspbian](https://www.raspberrypi.org/downloads/raspbian/)
  45. and the following setup
  46. * in the SD Cards's `/boot/config.txt` file `enable_uart=1` and `dtparam=spi=on`
  47. * [For flashrom](https://www.flashrom.org/RaspberryPi) we put `spi_bcm2835` and `spidev` in /etc/modules
  48. * [Connect to a wifi](https://www.raspberrypi.org/documentation/configuration/wireless/wireless-cli.md)
  49. * install `flashrom`
  50. * connect the Clip to the Raspberry Pi 3:
  51. Edge of pi (furthest from you)
  52. L CS
  53. E |
  54. F +---------------------------------------------------------------------------------+
  55. T | x x x x x x x x x x x x x x x x x x x x |
  56. | x x x x x x x x x x x x x x x x x x x x |
  57. E +----------------------------------^---^---^---^-------------------------------^--+
  58. D | | | | |
  59. G 3.3V MOSIMISO| GND
  60. E (VCC) CLK
  61. Body of Pi (closest to you)
  62. and you X230:
  63. Screen (furthest from you)
  64. __
  65. MOSI 5 --| |-- 4 GND
  66. CLK 6 --| |-- 3 N/C
  67. N/C 7 --| |-- 2 MISO
  68. VCC 8 --|__|-- 1 CS
  69. Edge (closest to you)
  70. Now you should be able to run the above mentioned `flashrom` commands.
  71. ## How we build
  72. Everything necessary to build coreboot is included in this project and building
  73. coreboot is not hard at all. Please refer to [coreboot's own documentation](https://www.coreboot.org/Build_HOWTO).
  74. When building, testing and doing a release here, we always try to upload our
  75. result to coreboot's [board status project](https://www.coreboot.org/Supported_Motherboards).