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@ -17,20 +17,17 @@ See our [releases](https://github.com/merge/coreboot-x230/releases) |
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That's the preferred way to use coreboot. The git revision we use is always included in the release. |
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### Intel microcode |
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* version [20180108](https://downloadcenter.intel.com/download/27431/Linux-Processor-Microcode-Data-File) |
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* in 20180108, for the X230's CPU ID (306ax) the latest update is 2015-02-26 |
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* (not yet in coreboot upstream) |
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* revision `1c` from 2015-02-26 (Intel package [20171117](https://downloadcenter.intel.com/download/27337) added by us; not yet in coreboot upstream) |
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### SeaBIOS |
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* version [1.11.0](https://seabios.org/Releases#SeaBIOS_1.11.0) from 2017-11-10 |
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* (in coreboot upstream) |
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* version [1.11.0](https://seabios.org/Releases#SeaBIOS_1.11.0) from 2017-11-10 (part of coreboot upstream) |
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## When do we do a release? |
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Either when |
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* There is a new SeaBIOS release, |
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* There is a new Intel microcode release (included in coreboot AND affecting our CPU ID), |
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* There is a coreboot issue that affects us (unlikely), or |
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* We need to change the config |
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* There is a coreboot issue that affects us, or |
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* We change the config |
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## TL;DR |
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Download a released image, connect your hardware SPI flasher to the "upper" |
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Martin Kepplinger
6 years ago