this actually got lost during updates for the release.

This feels like the last piece of the puzzle in chip-detection.

Fixes #82

me_cleaner says:
remove the ME/TXE Read/Write permissions to the other regions on the
flash from the Intel Flash Descriptor (requires a full dump).

Which sounds reasonable to do.

Fixes #76

For creating USB bios images from Lenovo's BIOS, we shouldn't duplicate
instructions. Things might change and break for users that way.

see #77

This makes things easier to maintain and simply causes less confusion
for users. We only want the lastest EC firmware.

Closes #77

While I think I have initially used 128 from some libreboot docs and never
had problems with it, I don't really see anybody use less than 512 right
now.

We recently added that the whole 8M chip flashing is optional, which is
important indeed. In brough some more stuff in which may be confusion.

We don't want to mention one specific OS because we're really generic
people should try to install whatever they want.

Also, "the command defaults to..." is misleading, as there are commandline
options applied in our example. Remove that.

And lastly, as long as users make the backups we always suggest in the
examples, they can change things at any time.

Despite I've never had any problems, applying external voltage to the
flash is considered dangerous, see #49 and #68. So change our documentation to
suggest not to do this often. Also, remove the note about "WoL power"
not being necessary. We don't document that (yet) anyways.

Fixes #68

see #65

Fixes #56
Closes #58

thanks @apraile from github.

see #21

an out-of-tree change is not needed anymore. coreboot upstream includes the
latest microcode updates we need.

the bootsplash image is added to the build.

see #21

in fact, detecting MX25L6406E/MX25L6408E has not worked. only EN25QH64
was detected because the former got overwritten. fix the logic and
detect either one.

Fixes #52
Closes #54

This fixes a memory leak and the output in case the flash chip is not
found by our scripts.

This simplifies setup by remove the unneeded RAM voltage checking.

According to the spec, DDR3L RAM has to work using 1.5V, see
https://en.wikipedia.org/wiki/DDR3_SDRAM#DDR3L_and_DDR3U_extensions.
Coreboot simply doesn't always implement changing voltage, which
can never prevent RAM from working though.

Closes #50
Fixes #38

First-time installation link was missing a dash

Closes #47

we require to rename one config for building for now

this simplifies the microcode pull-in

We already have a config for a more free version using SeaVGABIOS. From now
on we build, test and release that too. The image filename should just
contail _free_ which is probably enough.

Closes #32