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264 lines
9.4 KiB
264 lines
9.4 KiB
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __TIMESTAMP_SERIALIZED_H__
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#define __TIMESTAMP_SERIALIZED_H__
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#include <stdint.h>
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struct timestamp_entry {
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uint32_t entry_id;
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uint64_t entry_stamp;
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} __packed;
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struct timestamp_table {
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uint64_t base_time;
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uint16_t max_entries;
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uint16_t tick_freq_mhz;
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uint32_t num_entries;
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struct timestamp_entry entries[0]; /* Variable number of entries */
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} __packed;
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enum timestamp_id {
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TS_START_ROMSTAGE = 1,
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TS_BEFORE_INITRAM = 2,
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TS_AFTER_INITRAM = 3,
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TS_END_ROMSTAGE = 4,
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TS_START_VBOOT = 5,
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TS_END_VBOOT = 6,
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TS_START_COPYRAM = 8,
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TS_END_COPYRAM = 9,
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TS_START_RAMSTAGE = 10,
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TS_START_BOOTBLOCK = 11,
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TS_END_BOOTBLOCK = 12,
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TS_START_COPYROM = 13,
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TS_END_COPYROM = 14,
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TS_START_ULZMA = 15,
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TS_END_ULZMA = 16,
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TS_START_ULZ4F = 17,
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TS_END_ULZ4F = 18,
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TS_DEVICE_ENUMERATE = 30,
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TS_DEVICE_CONFIGURE = 40,
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TS_DEVICE_ENABLE = 50,
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TS_DEVICE_INITIALIZE = 60,
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TS_OPROM_INITIALIZE = 65,
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TS_OPROM_COPY_END = 66,
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TS_OPROM_END = 67,
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TS_DEVICE_DONE = 70,
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TS_CBMEM_POST = 75,
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TS_WRITE_TABLES = 80,
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TS_FINALIZE_CHIPS = 85,
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TS_LOAD_PAYLOAD = 90,
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TS_ACPI_WAKE_JUMP = 98,
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TS_SELFBOOT_JUMP = 99,
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TS_START_POSTCAR = 100,
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TS_END_POSTCAR = 101,
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/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
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TS_START_COPYVER = 501,
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TS_END_COPYVER = 502,
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TS_START_TPMINIT = 503,
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TS_END_TPMINIT = 504,
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TS_START_VERIFY_SLOT = 505,
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TS_END_VERIFY_SLOT = 506,
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TS_START_HASH_BODY = 507,
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TS_DONE_LOADING = 508,
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TS_DONE_HASHING = 509,
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TS_END_HASH_BODY = 510,
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TS_START_TPMPCR = 511,
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TS_END_TPMPCR = 512,
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TS_START_TPMLOCK = 513,
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TS_END_TPMLOCK = 514,
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TS_START_COPYVPD = 550,
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TS_END_COPYVPD_RO = 551,
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TS_END_COPYVPD_RW = 552,
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/* 900-920 reserved for vendorcode extensions (900-940: AMD AGESA) */
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TS_AGESA_INIT_RESET_START = 900,
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TS_AGESA_INIT_RESET_DONE = 901,
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TS_AGESA_INIT_EARLY_START = 902,
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TS_AGESA_INIT_EARLY_DONE = 903,
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TS_AGESA_INIT_POST_START = 904,
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TS_AGESA_INIT_POST_DONE = 905,
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TS_AGESA_INIT_ENV_START = 906,
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TS_AGESA_INIT_ENV_DONE = 907,
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TS_AGESA_INIT_MID_START = 908,
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TS_AGESA_INIT_MID_DONE = 909,
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TS_AGESA_INIT_LATE_START = 910,
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TS_AGESA_INIT_LATE_DONE = 911,
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TS_AGESA_INIT_RTB_START = 912,
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TS_AGESA_INIT_RTB_DONE = 913,
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TS_AGESA_INIT_RESUME_START = 914,
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TS_AGESA_INIT_RESUME_DONE = 915,
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TS_AGESA_S3_LATE_START = 916,
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TS_AGESA_S3_LATE_DONE = 917,
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TS_AGESA_S3_FINAL_START = 918,
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TS_AGESA_S3_FINAL_DONE = 919,
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/* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */
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TS_ME_INFORM_DRAM_WAIT = 940,
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TS_ME_INFORM_DRAM_DONE = 941,
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/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
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TS_FSP_MEMORY_INIT_START = 950,
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TS_FSP_MEMORY_INIT_END = 951,
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TS_FSP_TEMP_RAM_EXIT_START = 952,
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TS_FSP_TEMP_RAM_EXIT_END = 953,
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TS_FSP_SILICON_INIT_START = 954,
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TS_FSP_SILICON_INIT_END = 955,
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TS_FSP_BEFORE_ENUMERATE = 956,
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TS_FSP_AFTER_ENUMERATE = 957,
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TS_FSP_BEFORE_FINALIZE = 958,
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TS_FSP_AFTER_FINALIZE = 959,
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TS_FSP_BEFORE_END_OF_FIRMWARE = 960,
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TS_FSP_AFTER_END_OF_FIRMWARE = 961,
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/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
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/* Depthcharge entry IDs start at 1000 */
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TS_DC_START = 1000,
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TS_RO_PARAMS_INIT = 1001,
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TS_RO_VB_INIT = 1002,
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TS_RO_VB_SELECT_FIRMWARE = 1003,
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TS_RO_VB_SELECT_AND_LOAD_KERNEL = 1004,
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TS_RW_VB_SELECT_AND_LOAD_KERNEL = 1010,
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TS_VB_SELECT_AND_LOAD_KERNEL = 1020,
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TS_VB_EC_VBOOT_DONE = 1030,
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TS_VB_STORAGE_INIT_DONE = 1040,
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TS_VB_READ_KERNEL_DONE = 1050,
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TS_VB_VBOOT_DONE = 1100,
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TS_START_KERNEL = 1101,
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TS_KERNEL_DECOMPRESSION = 1102,
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};
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static const struct timestamp_id_to_name {
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uint32_t id;
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const char *name;
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} timestamp_ids[] = {
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/* Marker to report base_time. */
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{ 0, "1st timestamp" },
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{ TS_START_ROMSTAGE, "start of romstage" },
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{ TS_BEFORE_INITRAM, "before ram initialization" },
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{ TS_AFTER_INITRAM, "after ram initialization" },
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{ TS_END_ROMSTAGE, "end of romstage" },
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{ TS_START_VBOOT, "start of verified boot" },
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{ TS_END_VBOOT, "end of verified boot" },
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{ TS_START_COPYRAM, "starting to load ramstage" },
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{ TS_END_COPYRAM, "finished loading ramstage" },
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{ TS_START_RAMSTAGE, "start of ramstage" },
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{ TS_START_BOOTBLOCK, "start of bootblock" },
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{ TS_END_BOOTBLOCK, "end of bootblock" },
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{ TS_START_COPYROM, "starting to load romstage" },
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{ TS_END_COPYROM, "finished loading romstage" },
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{ TS_START_ULZMA, "starting LZMA decompress (ignore for x86)" },
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{ TS_END_ULZMA, "finished LZMA decompress (ignore for x86)" },
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{ TS_START_ULZ4F, "starting LZ4 decompress (ignore for x86)" },
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{ TS_END_ULZ4F, "finished LZ4 decompress (ignore for x86)" },
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{ TS_DEVICE_ENUMERATE, "device enumeration" },
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{ TS_DEVICE_CONFIGURE, "device configuration" },
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{ TS_DEVICE_ENABLE, "device enable" },
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{ TS_DEVICE_INITIALIZE, "device initialization" },
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{ TS_OPROM_INITIALIZE, "Option ROM initialization" },
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{ TS_OPROM_COPY_END, "Option ROM copy done" },
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{ TS_OPROM_END, "Option ROM run done" },
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{ TS_DEVICE_DONE, "device setup done" },
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{ TS_CBMEM_POST, "cbmem post" },
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{ TS_WRITE_TABLES, "write tables" },
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{ TS_FINALIZE_CHIPS, "finalize chips" },
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{ TS_LOAD_PAYLOAD, "load payload" },
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{ TS_ACPI_WAKE_JUMP, "ACPI wake jump" },
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{ TS_SELFBOOT_JUMP, "selfboot jump" },
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{ TS_START_COPYVER, "starting to load verstage" },
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{ TS_END_COPYVER, "finished loading verstage" },
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{ TS_START_TPMINIT, "starting to initialize TPM" },
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{ TS_END_TPMINIT, "finished TPM initialization" },
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{ TS_START_VERIFY_SLOT, "starting to verify keyblock/preamble (RSA)" },
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{ TS_END_VERIFY_SLOT, "finished verifying keyblock/preamble (RSA)" },
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{ TS_START_HASH_BODY, "starting to verify body (load+SHA2+RSA) " },
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{ TS_DONE_LOADING, "finished loading body (ignore for x86)" },
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{ TS_DONE_HASHING, "finished calculating body hash (SHA2)" },
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{ TS_END_HASH_BODY, "finished verifying body signature (RSA)" },
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{ TS_START_TPMPCR, "starting TPM PCR extend" },
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{ TS_END_TPMPCR, "finished TPM PCR extend" },
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{ TS_START_TPMLOCK, "starting locking TPM" },
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{ TS_END_TPMLOCK, "finished locking TPM" },
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{ TS_START_COPYVPD, "starting to load Chrome OS VPD" },
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{ TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" },
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{ TS_END_COPYVPD_RW, "finished loading Chrome OS VPD (RW)" },
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{ TS_DC_START, "depthcharge start" },
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{ TS_RO_PARAMS_INIT, "RO parameter init" },
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{ TS_RO_VB_INIT, "RO vboot init" },
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{ TS_RO_VB_SELECT_FIRMWARE, "RO vboot select firmware" },
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{ TS_RO_VB_SELECT_AND_LOAD_KERNEL, "RO vboot select&load kernel" },
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{ TS_RW_VB_SELECT_AND_LOAD_KERNEL, "RW vboot select&load kernel" },
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{ TS_VB_SELECT_AND_LOAD_KERNEL, "vboot select&load kernel" },
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{ TS_VB_EC_VBOOT_DONE, "finished EC verification" },
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{ TS_VB_STORAGE_INIT_DONE, "finished storage device initialization" },
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{ TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" },
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{ TS_VB_VBOOT_DONE, "finished vboot kernel verification" },
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{ TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" },
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{ TS_START_KERNEL, "jumping to kernel" },
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/* AMD AGESA related timestamps */
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{ TS_AGESA_INIT_RESET_START, "calling AmdInitReset" },
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{ TS_AGESA_INIT_RESET_DONE, "back from AmdInitReset" },
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{ TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" },
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{ TS_AGESA_INIT_EARLY_DONE, "back from AmdInitEarly" },
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{ TS_AGESA_INIT_POST_START, "calling AmdInitPost" },
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{ TS_AGESA_INIT_POST_DONE, "back from AmdInitPost" },
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{ TS_AGESA_INIT_ENV_START, "calling AmdInitEnv" },
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{ TS_AGESA_INIT_ENV_DONE, "back from AmdInitEnv" },
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{ TS_AGESA_INIT_MID_START, "calling AmdInitMid" },
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{ TS_AGESA_INIT_MID_DONE, "back from AmdInitMid" },
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{ TS_AGESA_INIT_LATE_START, "calling AmdInitLate" },
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{ TS_AGESA_INIT_LATE_DONE, "back from AmdInitLate" },
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{ TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save" },
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{ TS_AGESA_INIT_RTB_DONE, "back from AmdInitRtb/AmdS3Save" },
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{ TS_AGESA_INIT_RESUME_START, "calling AmdInitResume" },
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{ TS_AGESA_INIT_RESUME_DONE, "back from AmdInitResume" },
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{ TS_AGESA_S3_LATE_START, "calling AmdS3LateRestore" },
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{ TS_AGESA_S3_LATE_DONE, "back from AmdS3LateRestore" },
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{ TS_AGESA_S3_FINAL_START, "calling AmdS3FinalRestore" },
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{ TS_AGESA_S3_FINAL_DONE, "back from AmdS3FinalRestore" },
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/* Intel ME related timestamps */
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{ TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"},
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{ TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"},
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/* FSP related timestamps */
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{ TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" },
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{ TS_FSP_MEMORY_INIT_END, "returning from FspMemoryInit" },
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{ TS_FSP_TEMP_RAM_EXIT_START, "calling FspTempRamExit" },
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{ TS_FSP_TEMP_RAM_EXIT_END, "returning from FspTempRamExit" },
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{ TS_FSP_SILICON_INIT_START, "calling FspSiliconInit" },
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{ TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit" },
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{ TS_FSP_BEFORE_ENUMERATE, "calling FspNotify(AfterPciEnumeration)" },
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{ TS_FSP_AFTER_ENUMERATE,
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"returning from FspNotify(AfterPciEnumeration)" },
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{ TS_FSP_BEFORE_FINALIZE, "calling FspNotify(ReadyToBoot)" },
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{ TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" },
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{ TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" },
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{ TS_FSP_AFTER_END_OF_FIRMWARE,
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"returning from FspNotify(EndOfFirmware)" },
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{ TS_START_POSTCAR, "start of postcar" },
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{ TS_END_POSTCAR, "end of postcar" },
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};
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#endif
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