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@ -1,5 +1,5 @@ |
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/* |
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/* |
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio |
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio |
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Licensed under the Apache License, Version 2.0 (the "License"); |
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Licensed under the Apache License, Version 2.0 (the "License"); |
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you may not use this file except in compliance with the License. |
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you may not use this file except in compliance with the License. |
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@ -32,12 +32,7 @@ |
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#define MCUCONF_H |
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#define MCUCONF_H |
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#define STM32L4xx_MCUCONF |
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#define STM32L4xx_MCUCONF |
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#define STM32L412_MCUCONF |
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#define STM32L422_MCUCONF |
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#define STM32L422_MCUCONF |
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#define STM32L432_MCUCONF |
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#define STM32L433_MCUCONF |
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#define STM32L442_MCUCONF |
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#define STM32L443_MCUCONF |
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/* |
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/* |
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* HAL driver system settings. |
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* HAL driver system settings. |
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@ -52,16 +47,13 @@ |
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#define STM32_HSE_ENABLED FALSE |
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#define STM32_HSE_ENABLED FALSE |
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#define STM32_LSE_ENABLED FALSE |
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#define STM32_LSE_ENABLED FALSE |
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#define STM32_MSIPLL_ENABLED FALSE |
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#define STM32_MSIPLL_ENABLED FALSE |
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#define STM32_ADC_CLOCK_ENABLED TRUE |
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#define STM32_USB_CLOCK_ENABLED TRUE |
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#define STM32_SAI1_CLOCK_ENABLED TRUE |
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#define STM32_SAI2_CLOCK_ENABLED TRUE |
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#define STM32_MSIRANGE STM32_MSIRANGE_4M |
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#define STM32_MSIRANGE STM32_MSIRANGE_4M |
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#define STM32_MSISRANGE STM32_MSISRANGE_4M |
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#define STM32_MSISRANGE STM32_MSISRANGE_4M |
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#define STM32_SW STM32_SW_PLL |
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#define STM32_SW STM32_SW_PLL |
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#define STM32_PLLSRC STM32_PLLSRC_HSI16 |
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#define STM32_PLLSRC STM32_PLLSRC_HSI16 |
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#define STM32_PLLM_VALUE 4 |
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#define STM32_PLLM_VALUE 4 |
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#define STM32_PLLN_VALUE 80 |
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#define STM32_PLLN_VALUE 80 |
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#define STM32_PLLPDIV_VALUE 0 |
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#define STM32_PLLP_VALUE 7 |
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#define STM32_PLLP_VALUE 7 |
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#define STM32_PLLQ_VALUE 4 |
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#define STM32_PLLQ_VALUE 4 |
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#define STM32_PLLR_VALUE 4 |
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#define STM32_PLLR_VALUE 4 |
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@ -73,29 +65,22 @@ |
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#define STM32_MCOPRE STM32_MCOPRE_DIV1 |
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#define STM32_MCOPRE STM32_MCOPRE_DIV1 |
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK |
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK |
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#define STM32_PLLSAI1N_VALUE 72 |
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#define STM32_PLLSAI1N_VALUE 72 |
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#define STM32_PLLSAI1PDIV_VALUE 6 |
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#define STM32_PLLSAI1P_VALUE 7 |
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#define STM32_PLLSAI1P_VALUE 7 |
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#define STM32_PLLSAI1Q_VALUE 6 |
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#define STM32_PLLSAI1Q_VALUE 6 |
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#define STM32_PLLSAI1R_VALUE 6 |
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#define STM32_PLLSAI1R_VALUE 6 |
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#define STM32_PLLSAI2N_VALUE 72 |
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#define STM32_PLLSAI2P_VALUE 7 |
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#define STM32_PLLSAI2R_VALUE 6 |
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/* |
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/* |
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* Peripherals clock sources. |
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* Peripherals clock sources. |
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*/ |
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*/ |
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#define STM32_USART1SEL STM32_USART1SEL_SYSCLK |
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#define STM32_USART1SEL STM32_USART1SEL_SYSCLK |
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#define STM32_USART2SEL STM32_USART2SEL_SYSCLK |
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#define STM32_USART2SEL STM32_USART2SEL_SYSCLK |
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#define STM32_USART3SEL STM32_USART3SEL_SYSCLK |
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#define STM32_UART4SEL STM32_UART4SEL_SYSCLK |
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#define STM32_UART5SEL STM32_UART5SEL_SYSCLK |
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#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK |
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#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK |
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#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK |
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#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK |
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#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK |
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#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK |
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#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK |
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 |
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 |
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 |
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 |
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#define STM32_SAI1SEL STM32_SAI1SEL_OFF |
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#define STM32_SAI1SEL STM32_SAI1SEL_OFF |
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#define STM32_SAI2SEL STM32_SAI2SEL_OFF |
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#define STM32_CLK48SEL STM32_CLK48SEL_HSI48 |
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#define STM32_CLK48SEL STM32_CLK48SEL_HSI48 |
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK |
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK |
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 |
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 |
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@ -127,7 +112,6 @@ |
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#define STM32_IRQ_USART1_PRIORITY 12 |
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#define STM32_IRQ_USART1_PRIORITY 12 |
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#define STM32_IRQ_USART2_PRIORITY 12 |
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#define STM32_IRQ_USART2_PRIORITY 12 |
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#define STM32_IRQ_USART3_PRIORITY 12 |
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#define STM32_IRQ_LPUART1_PRIORITY 12 |
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#define STM32_IRQ_LPUART1_PRIORITY 12 |
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/* |
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/* |
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@ -137,29 +121,15 @@ |
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#define STM32_ADC_USE_ADC1 FALSE |
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#define STM32_ADC_USE_ADC1 FALSE |
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) |
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) |
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#define STM32_ADC_ADC1_DMA_PRIORITY 2 |
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#define STM32_ADC_ADC1_DMA_PRIORITY 2 |
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#define STM32_ADC_USE_ADC2 FALSE |
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#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
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#define STM32_ADC_ADC2_DMA_PRIORITY 2 |
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
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#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
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#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 |
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#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 |
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/* |
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* CAN driver system settings. |
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*/ |
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#define STM32_CAN_USE_CAN1 FALSE |
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#define STM32_CAN_CAN1_IRQ_PRIORITY 11 |
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/* |
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* DAC driver system settings. |
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*/ |
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#define STM32_DAC_DUAL_MODE FALSE |
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#define STM32_DAC_USE_DAC1_CH1 FALSE |
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#define STM32_DAC_USE_DAC1_CH2 FALSE |
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 |
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 |
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 |
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 |
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
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/* |
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/* |
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* GPT driver system settings. |
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* GPT driver system settings. |
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@ -198,7 +168,6 @@ |
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/* |
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/* |
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* PWM driver system settings. |
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* PWM driver system settings. |
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*/ |
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*/ |
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#define STM32_PWM_USE_ADVANCED FALSE |
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#define STM32_PWM_USE_TIM1 FALSE |
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#define STM32_PWM_USE_TIM1 FALSE |
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#define STM32_PWM_USE_TIM2 FALSE |
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#define STM32_PWM_USE_TIM2 FALSE |
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#define STM32_PWM_USE_TIM15 FALSE |
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#define STM32_PWM_USE_TIM15 FALSE |
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#define STM32_SERIAL_USE_USART1 FALSE |
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#define STM32_SERIAL_USE_USART1 FALSE |
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#define STM32_SERIAL_USE_USART2 FALSE |
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#define STM32_SERIAL_USE_USART2 FALSE |
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#define STM32_SERIAL_USE_LPUART1 FALSE |
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#define STM32_SERIAL_USE_LPUART1 FALSE |
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#define STM32_SERIAL_USART1_PRIORITY 12 |
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#define STM32_SERIAL_USART2_PRIORITY 12 |
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#define STM32_SERIAL_LPUART1_PRIORITY 12 |
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/* |
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* SIO driver system settings. |
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*/ |
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#define STM32_SIO_USE_USART1 FALSE |
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#define STM32_SIO_USE_USART2 FALSE |
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#define STM32_SIO_USE_LPUART1 FALSE |
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/* |
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/* |
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* SPI driver system settings. |
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* SPI driver system settings. |
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*/ |
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*/ |
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#define STM32_SPI_USE_SPI1 FALSE |
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#define STM32_SPI_USE_SPI1 FALSE |
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#define STM32_SPI_USE_SPI3 FALSE |
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) |
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
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#define STM32_SPI_SPI1_DMA_PRIORITY 1 |
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#define STM32_SPI_SPI1_DMA_PRIORITY 1 |
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#define STM32_SPI_SPI3_DMA_PRIORITY 1 |
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10 |
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
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/* |
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/* |
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