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41 lines
1.3 KiB
41 lines
1.3 KiB
#pragma once
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#ifdef PS2_DRIVER_USART
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#define PS2_CLOCK_PIN D5
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#define PS2_DATA_PIN D2
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/* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
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/* set DDR of CLOCK as input to be slave */
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#define PS2_USART_INIT() do { \
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PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
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PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
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UCSR1C = ((1 << UMSEL10) | \
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(3 << UPM10) | \
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(0 << USBS1) | \
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(3 << UCSZ10) | \
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(0 << UCPOL1)); \
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UCSR1A = 0; \
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UBRR1H = 0; \
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UBRR1L = 0; \
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} while (0)
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#define PS2_USART_RX_INT_ON() do { \
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UCSR1B = ((1 << RXCIE1) | \
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(1 << RXEN1)); \
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} while (0)
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#define PS2_USART_RX_POLL_ON() do { \
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UCSR1B = (1 << RXEN1); \
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} while (0)
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#define PS2_USART_OFF() do { \
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UCSR1C = 0; \
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UCSR1B &= ~((1 << RXEN1) | \
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(1 << TXEN1)); \
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} while (0)
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#define PS2_USART_RX_READY (UCSR1A & (1<<RXC1))
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#define PS2_USART_RX_DATA UDR1
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#define PS2_USART_ERROR (UCSR1A & ((1<<FE1) | (1<<DOR1) | (1<<UPE1)))
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#define PS2_USART_RX_VECT USART1_RX_vect
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#endif
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#define LOCKING_SUPPORT_ENABLE
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#define LOCKING_RESYNC_ENABLE
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