Despite I've never had any problems, applying external voltage to the
flash is considered dangerous, see #49 and #68. So change our documentation to
suggest not to do this often. Also, remove the note about "WoL power"
not being necessary. We don't document that (yet) anyways.

Fixes #68

see #65

Fixes #56
Closes #58

thanks @apraile from github.

see #21

an out-of-tree change is not needed anymore. coreboot upstream includes the
latest microcode updates we need.

the bootsplash image is added to the build.

see #21

in fact, detecting MX25L6406E/MX25L6408E has not worked. only EN25QH64
was detected because the former got overwritten. fix the logic and
detect either one.

Fixes #52
Closes #54

This fixes a memory leak and the output in case the flash chip is not
found by our scripts.

This simplifies setup by remove the unneeded RAM voltage checking.

According to the spec, DDR3L RAM has to work using 1.5V, see
https://en.wikipedia.org/wiki/DDR3_SDRAM#DDR3L_and_DDR3U_extensions.
Coreboot simply doesn't always implement changing voltage, which
can never prevent RAM from working though.

Closes #50
Fixes #38

First-time installation link was missing a dash

Closes #47

we require to rename one config for building for now

this simplifies the microcode pull-in

We already have a config for a more free version using SeaVGABIOS. From now
on we build, test and release that too. The image filename should just
contail _free_ which is probably enough.

Closes #32

It feelds a little more streamlined when not repeating everything the
user does.

We rebased commit ([WIP] 3rdparty/blobs: Bump for new microcode update for
Intel model 306ax) to the current coreboot master state fb758d420b and
update our build scripts.

We run oldconfig on our config and update it.